/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 256 176)
	(text "ad7301_controller" (rect 5 0 91 12)(font "Arial" ))
	(text "inst" (rect 8 144 25 156)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "reset_" (rect 0 0 30 12)(font "Arial" ))
		(text "reset_" (rect 21 27 51 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "CLK_66M" (rect 0 0 47 12)(font "Arial" ))
		(text "CLK_66M" (rect 21 43 68 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 0 64)
		(input)
		(text "sample_start" (rect 0 0 63 12)(font "Arial" ))
		(text "sample_start" (rect 21 59 84 71)(font "Arial" ))
		(line (pt 0 64)(pt 16 64)(line_width 1))
	)
	(port
		(pt 0 80)
		(input)
		(text "fifo_usedw[7..0]" (rect 0 0 80 12)(font "Arial" ))
		(text "fifo_usedw[7..0]" (rect 21 75 101 87)(font "Arial" ))
		(line (pt 0 80)(pt 16 80)(line_width 3))
	)
	(port
		(pt 0 96)
		(input)
		(text "DOUT" (rect 0 0 30 12)(font "Arial" ))
		(text "DOUT" (rect 21 91 51 103)(font "Arial" ))
		(line (pt 0 96)(pt 16 96)(line_width 1))
	)
	(port
		(pt 240 32)
		(output)
		(text "SCLK" (rect 0 0 28 12)(font "Arial" ))
		(text "SCLK" (rect 191 27 219 39)(font "Arial" ))
		(line (pt 240 32)(pt 224 32)(line_width 1))
	)
	(port
		(pt 240 48)
		(output)
		(text "ad7301_channel[2..0]" (rect 0 0 105 12)(font "Arial" ))
		(text "ad7301_channel[2..0]" (rect 114 43 219 55)(font "Arial" ))
		(line (pt 240 48)(pt 224 48)(line_width 3))
	)
	(port
		(pt 240 64)
		(output)
		(text "ad7301_data[15..0]" (rect 0 0 94 12)(font "Arial" ))
		(text "ad7301_data[15..0]" (rect 125 59 219 71)(font "Arial" ))
		(line (pt 240 64)(pt 224 64)(line_width 3))
	)
	(port
		(pt 240 80)
		(output)
		(text "fifo_write" (rect 0 0 46 12)(font "Arial" ))
		(text "fifo_write" (rect 173 75 219 87)(font "Arial" ))
		(line (pt 240 80)(pt 224 80)(line_width 1))
	)
	(port
		(pt 240 96)
		(output)
		(text "state[15..0]" (rect 0 0 56 12)(font "Arial" ))
		(text "state[15..0]" (rect 163 91 219 103)(font "Arial" ))
		(line (pt 240 96)(pt 224 96)(line_width 3))
	)
	(port
		(pt 240 112)
		(output)
		(text "DIN" (rect 0 0 20 12)(font "Arial" ))
		(text "DIN" (rect 199 107 219 119)(font "Arial" ))
		(line (pt 240 112)(pt 224 112)(line_width 1))
	)
	(drawing
		(rectangle (rect 16 16 224 144)(line_width 1))
	)
)