?? _back_fifo_waveforms.html
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<title>Sample Waveforms for _back_fifo.v </title>
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<h2><CENTER>Sample behavioral waveforms for design file _back_fifo.v </CENTER></h2>
<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design _back_fifo.v. The design _back_fifo.v has a depth of 2048 words of 16 bits each. The output of the fifo is registered. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
<CENTER><img src=_back_fifo_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
<CENTER><img src=_back_fifo_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design for FIFO full condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P>
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