module NUM_TEST1(reset_,sclk,num);input reset_,sclk;output [31:0]num;reg [31:0]num;
reg [3:0]counter;always @(posedge sclk or negedge reset_)begin
	if(!reset_)	begin
		num<= 32'd0;
		counter <= 4'd1;
	end
	else if(counter[3])	
	begin num<=num+ 32'd1;	counter[3] <= 1'b0;	counter[0]<=1'b1;end
	else counter <= counter + 4'd1;
endendmodule