module DS_ad_ctrl (	reset,ds_clk,sample_start,ad_read,ad_eoc,ad_cs,ad_conv,max_sel,
					ad_sel1,ad_sel2,ad_sel3,ad_sel4,busy,ram_addr,fifo_data,ram_ce1,ram_ce2,ram_we,ram_oe,
					ad_data,state,fifo_write,zijian_ctrl,SCLK,busy_flag_en,counter_busy);
					
	input reset, ds_clk, sample_start, ad_eoc,busy;
	input [11:0]ad_data;
	output[3:0] max_sel,state;
	output ad_read, ad_sel1,ad_sel2, ad_sel3,ad_sel4,ad_conv,ad_cs;
	output [20:0]ram_addr;
	output [15:0]fifo_data;
	output ram_ce1,ram_ce2,ram_we,ram_oe,fifo_write;
	output [9:0] zijian_ctrl;
	reg [15:0]data;
	reg [20:0]addr;
	wire ad_cs;
	wire ad_read;
	wire [2:0] max_sel;
	wire ad_sel1,ad_sel2,ad_sel3,ad_sel4, ad_conv,ram_write;
	wire [3:0] state;
	wire fifo_write;
	wire [9:0] zijian_ctrl;
	//reg [7:0] ds_testData;
	wire [15:0] fifo_data;
	//reg [15:0] data_buf;
	output SCLK;
	reg SCLK;	
	
	//需要3000分頻,每個周期=30ns*3000=90us=0.09ms，則每18和周期對應(yīng)4個數(shù)據(jù)，1.62ms對應(yīng)4個數(shù)據(jù)
		//則128個數(shù)據(jù)需要51.84ms
	parameter [11:0] num1 = 12'd1500;//1500;//101_1101_1100;//1500
	parameter [11:0] num2 = 12'd2999;//3000;//1011_1011_1000;//3000
	output busy_flag_en;
	reg busy_flag_en;
	reg [11:0] counter;
	output [13:0] counter_busy;
	reg [13:0] counter_busy;  //10_1110_1110_0000
	always @(posedge ds_clk or negedge reset)begin
		if(!reset) begin
			counter <= 13'd0;
			SCLK <= 1'b0;
		end
		else begin
			if(counter <= num1)begin
				counter <= counter + 12'd1;
				SCLK <= 1'b0;
			end
			else if (counter <= num2)begin
				counter <= counter + 12'd1;
				SCLK <= 1'b1;
			end
			else begin
				counter <= 13'd0;
			end
		end
	end
	
	always @(posedge ds_clk or negedge reset)begin
		if(!reset) begin
			counter_busy <= 14'd0;
			busy_flag_en <= 1'b0;
		end
		else begin
			if(counter_busy <= 14'd12000)begin
				counter_busy <= counter_busy + 14'd1;
				if(busy == 1'b1)begin
					busy_flag_en <= 1'b1;
				end
			end
			else begin
				counter_busy <= 14'd0;
				busy_flag_en <= 1'b0;
			end
		end
	end
	
	/*always @(posedge ds_clk or negedge reset)begin
		if(!reset) begin
			busy_flag_en <= 1'b0;
		end
		else begin	
			if((busy == 1'b1)&&(counter_busy < num2))begin
				busy_flag_en <= 1'b1;
			end
			else if (counter == num2)begin
				busy_flag_en <= 1'b0;
			end
		end
	end*/
//////////////////////////////////////////////////////////////////////////////////////////////
DS_ad_subctrl   DS_ad_subctrl (	.reset(reset),
					.S_CLK(SCLK),
					.sample_start(sample_start),
					.ad_read(ad_read),
					.ad_eoc(ad_eoc),
					.ad_cs(ad_cs),
					.ad_conv(ad_conv),
					.max_sel(max_sel),
					.ad_sel1(ad_sel1),
					.ad_sel2(ad_sel2),
					.ad_sel3(ad_sel3),
					.ad_sel4(ad_sel4),
					.busy(busy_flag_en),
					.ram_addr(ram_addr),
					.fifo_data(fifo_data),
					.ram_ce1(ram_ce1),
					.ram_ce2(ram_ce2),
					.ram_we(ram_we),
					.ram_oe(ram_oe),
					.ad_data(ad_data),
					.state(state),
					.fifo_write(fifo_write),
					.zijian_ctrl(zijian_ctrl)
					);				
endmodule