module ad7864_controller(reset_,
CLK_66M,
sample_start,
ad_conv,
ad_cs,
ad_read,
ad_busy,
ad_data,
fifo_data,
fifo_write,
fifo_usedw,
state,
ad_busy_flag
);
input reset_;
input CLK_66M;
input sample_start;
input ad_busy;
input [11:0] ad_data;
input [8:0] fifo_usedw;

output ad_conv;
reg ad_conv;
output ad_cs;
reg ad_cs;
output ad_read;
reg ad_read;
output [15:0] fifo_data;
reg [15:0] fifo_data;
output fifo_write;
reg fifo_write;
output [15:0] state;
reg [15:0] state;
output ad_busy_flag;
wire ad_busy_flag;

reg work_ena;
reg [15:0] fifo_data_buf;

assign ad_busy_flag = ad_busy;
always @(posedge CLK_66M or negedge reset_)begin
	if(!reset_) begin
		ad_conv <= 1'b1;
		ad_cs <= 1'b1;
		ad_read <= 1'b1;
		fifo_write <= 1'b0;
		state <= 16'h0;
		work_ena <= 1'b0;
		fifo_data <= 16'h0;
	end
	else begin
		if (!sample_start) begin
		case(state)
			16'd0:begin
				if(fifo_usedw[8] && fifo_usedw[7] && fifo_usedw[6]) begin
					work_ena <= 1'b0;
				end
				else begin
					work_ena <= 1'b1;
				end
				ad_conv <= 1'b1;
				ad_cs <= 1'b1;
				ad_read <= 1'b1;
				fifo_write <= 1'b0;
				state <= state + 16'd1;
			end
			16'd66:begin
				if(fifo_usedw[8] && fifo_usedw[7] && fifo_usedw[6]) begin
					work_ena <= 1'b0;
					state <= 16'd0;
				end
				else begin
					work_ena <= 1'b1;
					state <= state + 16'd1;
				end
			end
			16'd67:begin
				if(work_ena)begin
					ad_conv <= 1'b0;
					state <= state + 16'd1;
				end
				else begin
					state <= 16'd0;
				end
			end
			16'd180:begin
				ad_conv <= 1'b1;
				state <= state + 16'd1;
			end
			16'd220:begin
				if(ad_busy)begin
					state <= state + 16'd1;
				end
				else begin
					state <= 16'd0;
				end
			end
			16'd700:begin  //開始準備獲得數據
				fifo_data <= 16'h0;
				if(!ad_busy)begin
					ad_cs <= 1'b0;
					ad_read <= 1'b0;
					state <= state + 16'd1;
				end
				else begin
					ad_cs <= 1'b1;
					ad_read <= 1'b1;
					state <= state;
				end
			end
			16'd732:begin
				ad_cs <= 1'b1;
				ad_read <= 1'b1;
				fifo_data_buf <= {2'b11,2'b00,ad_data[11:0]};//read the first data
				state <= state + 16'd1;
			end
			17'd740:begin
				fifo_data <= fifo_data_buf;
				state <= state + 16'd1;
			end
			16'd748:begin
				//fifo_data <= fifo_data_buf;
				fifo_write <= 1'b1;
				state <= state + 16'd1;
			end
			16'd764:begin
				fifo_write <= 1'b0;
				ad_cs <= 1'b0;
				ad_read <= 1'b0;
				state <= state + 16'd1;
			end
			16'd796:begin
				ad_cs <= 1'b1;
				ad_read <= 1'b1;
				fifo_data_buf <= {2'b11,2'b01,ad_data[11:0]};//read the second data
				state <= state + 16'd1;
			end
			16'd804:begin
				fifo_data <= fifo_data_buf;
				state <= state + 16'd1;
			end
			16'd812:begin
				//fifo_data <= fifo_data_buf;
				fifo_write <= 1'b1;
				state <= state + 16'd1;
			end
			17'd828:begin
				fifo_write <= 1'b0;
				ad_cs <= 1'b0;
				ad_read <= 1'b0;
				state <= state + 16'd1;
			end
			16'd860:begin
				ad_cs <= 1'b1;
				ad_read <= 1'b1;
				fifo_data_buf <= {2'b11,2'b10,ad_data[11:0]};//read the third data
				state <= state + 16'd1;
			end
			16'd868:begin
				fifo_data <= fifo_data_buf;
				state <= state + 16'd1;
			end
			16'd876:begin
				//fifo_data <= fifo_data_buf;
				fifo_write <= 1'b1;
				state <= state + 16'd1;
			end
			17'd892:begin
				fifo_write <= 1'b0;
				ad_cs <= 1'b0;
				ad_read <= 1'b0;
				state <= state + 16'd1;
			end
			16'd924:begin
				ad_cs <= 1'b1;
				ad_read <= 1'b1;
				fifo_data_buf <= {2'b11,2'b11,ad_data[11:0]};//read the forth data
				state <= state + 16'd1;
			end
			16'd932:begin
				fifo_data <= fifo_data_buf;
				state <= state + 16'd1;
			end
			16'd940:begin
				//fifo_data <= fifo_data_buf;
				fifo_write <= 1'b1;
				state <= state + 16'd1;
			end
			16'd956:begin
				fifo_write <= 1'b0;
				ad_cs <= 1'b1;
				ad_read <= 1'b1;
				state <= state + 16'd1;
				//fifo_data <= 16'h0;
			end
			16'd996:begin
				state <= state + 16'd1;
				fifo_data <= 16'h0;
			end
			default:begin
				state <= state + 16'd1;
			end
		endcase	
		end
	end
end

endmodule 
/*
不管采樣率是多少，時鐘周期
經過32個周期，計數1ffff次，需要131071*15.15ns = 1.98572565ms
首先開始，復位之后先停頓1us，判斷FIFO是否足夠500個數據
	如果足夠，則邏輯停止
	否則，邏輯繼續工作
發出conv信號，持續150ns，10個周期
等待7.14us=500*15.15ns
1.發出CS_和RD_，
等待32個周期，
收回CS和RD，并讀取數據
等待16個周期，寫FIFO
2.等待16個周期，收回寫FIFO信號，發出CS_和RD_
等待32個周期，
收回CS和RD，并讀取數據
等待16個周期，寫FIFO
3.等待16個周期，收回寫FIFO信號，發出CS_和RD_
等待32個周期，
收回CS和RD，并讀取數據
等待16個周期，寫FIFO
4.等待16個周期，收回寫FIFO信號，發出CS_和RD_
等待32個周期，
收回CS和RD，并讀取數據
等待16個周期，寫FIFO
等待16個周期，收回寫FIFO信號
一直計數到本次周期結束
*/