module write_ram(		write_ram_start,		read_ram_start,		CLK,		reset_,//		LD,		ram_data,		data_en,		data_input,		o_ram_data,		ram_data_buf,
		counter_output,		ram_addr,				ram_ce1_,		ram_ce2,		ram_we_,		ram_bhe_,		ram_ble_,		);input write_ram_start;input read_ram_start;input CLK;input reset_;inout [15:0] ram_data;output [19:0] ram_addr;output data_en;output data_input;output [15:0] o_ram_data;output [15:0] ram_data_buf;output ram_ce2;output ram_ce1_;output ram_we_;output ram_bhe_;output ram_ble_;
output [19:0] counter_output;//inout [15:0] LD;reg [19:0] ram_addr;wire [15:0] ram_data;reg ram_ce1_;reg ram_ce2;reg ram_we_;reg ram_bhe_;reg ram_ble_;wire [19:0] counter_output;reg data_input;///////////////assign compatible logic////////////////wire [15:0] LD;wire [15:0] o_ram_data;assign o_ram_data = (data_en)?ram_data_buf:16'hz;//(data_en)?:16'hz;assign ram_data = (data_en)?ram_data_buf:16'hz;
assign counter_output = ram_counter;//assign LD = (data_input)?ram_addr:16'hz;///////////////////////////////////////////////////////////////////define reg to use///////////////reg [15:0] ram_data_buf;reg data_en;reg [1:0] operate_state;reg [19:0] ram_counter;reg [19:0] ram_counter1;//reg operate_state_read;reg write_ram_start_flag;
//reg read_ram_start_flag;parameter ram_num = 20'd1000;///////////////////////////////////////////////always @ (negedge CLK or negedge reset_)//因為PCI的DMA是上升沿采數(shù)，所以這里CLK使用下降沿作為觸發(fā)時鐘沿begin	if(!reset_)begin		ram_data_buf <= 16'h2000;		data_en <= 1'b0;		//ram_data <= 16'h0;		ram_ce1_ <= 1'b1;		ram_ce2 <= 1'b0;		ram_we_ <= 1'b1;		ram_bhe_ <= 1'b0;		ram_ble_ <= 1'b0;		ram_counter <= 20'd0;		ram_counter1 <= 20'd1;		operate_state <= 2'd0;		//ram_data <= 16'b0;		data_input <= 1'b0;		//operate_state_read <= 1'b0;	end	else begin		//		if (read_ram_start == 1) begin			ram_addr <= ram_counter1;			ram_counter1 <= ram_counter1 + 16'b01;			//LD <= ram_data;			data_input <= 1'b1;			data_en <= 1'b0;			/*if(ram_counter1 < ram_counter)begin				ram_counter1 <= ram_counter1 + 16'b1;			end			else begin				ram_counter1 <= ram_counter1;			end*/		end		else if(write_ram_start_flag && ram_counter <= 20'h2000)begin			data_input <= 1'b0;
			data_en <= 1'b1;			casex(operate_state)			2'd0:begin				ram_addr <= ram_counter + 20'd1;				ram_data_buf <= ram_data_buf - 16'd1;				ram_counter <= ram_counter + 20'd1;
				//data_en <= 1'b1;				operate_state <= 2'd1;			end			2'd1:begin				ram_ce1_ <= 1'b0;				//ram_data <= ram_data + 16'b1;				ram_ce2 <= 1'b1;				ram_we_ <= 1'b0;				//data_en <= 1'b1;				operate_state <= 2'd2;			end			2'd2:begin				//ram_ce1_ <= 1'b1;				//ram_ce2 <= 1'b0;				//ram_we_ <= 1'b1;				operate_state <= 2'd3;			end			2'd3:begin
				ram_ce1_ <= 1'b1;
				ram_ce2 <= 1'b0;				data_en <= 1'b1;
				ram_we_ <= 1'b1;				//ram_data <= 16'b0;				operate_state <= 2'd0;			end			endcase		end		/*else if (read_ram_start == 1) begin			ram_addr <= ram_counter1;			//ram_counter1 <= ram_counter1 + 16'b1;			if(ram_counter1 < ram_counter)begin				ram_counter1 <= ram_counter1 + 16'b1;			end			else begin				ram_counter1 <= ram_counter1;			end		end*/		else begin//修改之后，寫到最后一個地址之后就不進行任何操作了			data_en <= 1'b0;			data_input <= 1'b0;			//ram_data <= 16'h0;			ram_ce1_ <= 1'b0;			ram_ce2 <= 1'b1;			ram_we_ <= 1'b1;			ram_bhe_ <= 1'b0;			ram_ble_ <= 1'b0;			//ram_counter <= 20'd0;			//operate_state <= 2'd0;			//ram_data_buf <= 16'h0;		end	endendalways @ (posedge write_ram_start or negedge reset_)begin	if(!reset_)begin		write_ram_start_flag <= 1'b0;	end	else begin		write_ram_start_flag <= ~write_ram_start_flag;	endend
/*always @ (posedge read_ram_start or negedge reset_)
begin
	if(!reset_)begin
		read_ram_start_flag <= 1'b0;
	end
	else begin
		read_ram_start_flag <= ~write_ram_start_flag;
	end
end*/endmodule