//Author:liutong
//function: to receive serial data according to uart protocol
//16倍時(shí)鐘輸入，這樣可以每位數(shù)據(jù)多次采樣，增加采集數(shù)據(jù)的可靠性
module lt_uart_r5(sdin,clk16x,rst,r_enable,data_out,wrn);
input sdin,clk16x,rst,r_enable;

output [7:0]data_out;
output wrn;

reg [3:0]clk_count;//1倍時(shí)鐘的計(jì)數(shù)器
reg clk_enable;//中間時(shí)鐘使能
reg [2:0]in_count;//檢驗(yàn)是否是起始位時(shí)&數(shù)據(jù)讀取時(shí)作為計(jì)數(shù)器用
reg [2:0]_count1;
reg [2:0]_count0;

reg wrn;//數(shù)據(jù)好時(shí)，wrn輸出一個(gè)上升沿有效
reg [1:0]add;
reg [9:0]d;
reg [7:0]data_out;
reg [3:0]count;

always @(posedge clk16x or negedge rst)
begin
	if(!rst)
	begin	
		in_count<=3'b0;
		_count1<=3'b0;
		_count0<=3'b0;
		clk_enable<=1'b0;
		add<=2'b0;
		wrn<=1'b0;
		d<=10'b0;
		data_out<=8'b0;
		count<=4'b0;
		clk_count<=4'b1011;
	end
	else 
	begin
		if(clk_enable)	clk_count<=clk_count+4'd1;
		case(add)
		'b00:
		begin
			wrn<=1'b0;
			if (in_count==7)
			begin
				add<=2'b01;
				clk_enable<=1;
				in_count<=0;
			end
			else if(sdin==0)	in_count<=in_count+3'd1;
			else if(sdin==1)	in_count<=0;
		end
		'b01:	if(clk_count==4'b0111)	add<=2'b10;
		'b10:
		begin		
			if(count==8)
				begin		
					data_out[0]<=d[7];	data_out[1]<=d[6];	data_out[2]<=d[5];	data_out[3]<=d[4];
					data_out[4]<=d[3];	data_out[5]<=d[2];	data_out[6]<=d[1];	data_out[7]<=d[0];
				end
			if(count==9)
			begin
				if((d[0]==1)&&(r_enable==1))	
				begin		
					wrn<=1'b1;	
					count<=0; clk_enable<=0;	clk_count<=4'b1011;	add<=2'b0;
				end
			end
			/*
			if(count==10)
			begin
				if((d[0]==1)&&(^d==1)&&(r_enable==1))	
				begin		
					wrn<=1'b1;	
					count<=0; clk_enable<=0;	clk_count<='b1011;	add<=2'b0;
				end
			end
			*/
			else 
			begin
				if(in_count==7)	
				begin
					d[9:0]<={d[8:0],((_count1>=_count0)?1'b1:1'b0)};
					_count1<=3'b0;
					_count0<=3'b0;
					count<=count+4'd1;
					in_count<=3'b0;
				end
				else if(clk_count[3]==1)	
				begin 
					in_count<=in_count+3'd1;
					if(sdin)	_count1<=_count1+3'd1;	
					else _count0<=_count0+3'd1;
				end
				else
				begin
					_count1<=3'b0;
					_count0<=3'b0;
				end
			end
		end
		endcase
	end		
end
endmodule