?? ad_test.fit.rpt
字號:
Fitter report for ad_test
Mon Mar 23 21:53:47 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Partition Preservation Settings
5. Pin-Out File
6. Fitter Resource Usage Summary
7. Input Pins
8. Output Pins
9. Bidir Pins
10. I/O Bank Usage
11. All Package Pins
12. PLL Summary
13. PLL Usage
14. Output Pin Default Load For Reported TCO
15. Fitter Resource Utilization by Entity
16. Delay Chain Summary
17. Pad To Core Delay Chain Fanout
18. Control Signals
19. Global & Other Fast Signals
20. Non-Global High Fan-Out Signals
21. Fitter RAM Summary
22. Interconnect Usage Summary
23. LAB Logic Elements
24. LAB-wide Signals
25. LAB Signals Sourced
26. LAB Signals Sourced Out
27. LAB Distinct Inputs
28. Fitter Device Options
29. Fitter Messages
30. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------+
; Fitter Status ; Successful - Mon Mar 23 21:53:47 2009 ;
; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name ; ad_test ;
; Top-level Entity Name ; CPCI_exp ;
; Family ; Cyclone ;
; Device ; EP1C6Q240C7 ;
; Timing Models ; Final ;
; Total logic elements ; 1,478 / 5,980 ( 25 % ) ;
; Total pins ; 145 / 185 ( 78 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 65,536 / 92,160 ( 71 % ) ;
; Total PLLs ; 1 / 2 ( 50 % ) ;
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