--a_dpfifo ADD_RAM_OUTPUT_REGISTER="ON" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=512 LPM_SHOWAHEAD="ON" lpm_width=8 lpm_widthu=9 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock data empty full q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 8.0 cbx_altdpram 2008:03:07:257777 cbx_altsyncram 2008:03:26:267331 cbx_cycloneii 2008:02:23:252825 cbx_fifo_common 2008:02:23:252825 cbx_lpm_add_sub 2008:03:09:257947 cbx_lpm_compare 2008:02:23:252825 cbx_lpm_counter 2008:02:23:252825 cbx_lpm_decode 2008:02:23:252825 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944 cbx_scfifo 2008:02:23:252825 cbx_stratix 2008:02:23:252825 cbx_stratixii 2008:02:23:252825 cbx_stratixiii 2008:04:23:278548 cbx_util_mgl 2008:04:15:275689  VERSION_END


-- Copyright (C) 1991-2008 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.


FUNCTION altsyncram_boa1 (address_a[8..0], address_b[8..0], clock0, clock1, clocken1, data_a[7..0], wren_a)
RETURNS ( q_b[7..0]);
FUNCTION cntr_vbb (aclr, clock, cnt_en, sclr)
RETURNS ( q[7..0]);
FUNCTION cntr_cc7 (aclr, clock, cnt_en, sclr, updown)
RETURNS ( q[8..0]);
FUNCTION cntr_0cb (aclr, clock, cnt_en, sclr)
RETURNS ( q[8..0]);

--synthesis_resources = lut 29 
SUBDESIGN a_dpfifo_ai31
( 
	aclr	:	input;
	clock	:	input;
	data[7..0]	:	input;
	empty	:	output;
	full	:	output;
	q[7..0]	:	output;
	rreq	:	input;
	sclr	:	input;
	usedw[8..0]	:	output;
	wreq	:	input;
) 
VARIABLE 
	FIFOram : altsyncram_boa1;
	empty_dff : dffe;
	full_dff : dffe;
	low_addressa[8..0] : dffe;
	rd_ptr_lsb : dffe;
	usedw_is_0_dff : dffe;
	usedw_is_1_dff : dffe;
	usedw_is_2_dff : dffe;
	wrreq_delaya[1..0] : dffe;
	almost_full_comparer_aeb_int	:	WIRE;
	almost_full_comparer_aeb	:	WIRE;
	almost_full_comparer_dataa[8..0]	:	WIRE;
	almost_full_comparer_datab[8..0]	:	WIRE;
	three_comparison_aeb_int	:	WIRE;
	three_comparison_aeb	:	WIRE;
	three_comparison_dataa[8..0]	:	WIRE;
	three_comparison_datab[8..0]	:	WIRE;
	rd_ptr_msb : cntr_vbb;
	usedw_counter : cntr_cc7;
	wr_ptr : cntr_0cb;
	asynch_read_counter_enable	: WIRE;
	empty_out	: WIRE;
	full_out	: WIRE;
	pulse_ram_output	: WIRE;
	ram_read_address[8..0]	: WIRE;
	rd_ptr[8..0]	: WIRE;
	usedw_is_0	: WIRE;
	usedw_is_1	: WIRE;
	usedw_is_2	: WIRE;
	usedw_will_be_0	: WIRE;
	usedw_will_be_1	: WIRE;
	usedw_will_be_2	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;
	wait_state	: WIRE;

BEGIN 
	FIFOram.address_a[] = wr_ptr.q[];
	FIFOram.address_b[] = ram_read_address[];
	FIFOram.clock0 = clock;
	FIFOram.clock1 = clock;
	FIFOram.clocken1 = pulse_ram_output;
	FIFOram.data_a[] = data[];
	FIFOram.wren_a = valid_wreq;
	empty_dff.clk = clock;
	empty_dff.clrn = (! aclr);
	empty_dff.d = ((! (usedw_will_be_0 # wait_state)) & (! sclr));
	full_dff.clk = clock;
	full_dff.clrn = (! aclr);
	full_dff.d = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer_aeb) # (full_dff.q & (! (valid_wreq $ valid_rreq)))));
	low_addressa[].clk = clock;
	low_addressa[].clrn = (! aclr);
	low_addressa[].d = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].q)));
	rd_ptr_lsb.clk = clock;
	rd_ptr_lsb.clrn = (! aclr);
	rd_ptr_lsb.d = ((! rd_ptr_lsb.q) & (! sclr));
	rd_ptr_lsb.ena = (asynch_read_counter_enable # sclr);
	usedw_is_0_dff.clk = clock;
	usedw_is_0_dff.clrn = (! aclr);
	usedw_is_0_dff.d = (! usedw_will_be_0);
	usedw_is_1_dff.clk = clock;
	usedw_is_1_dff.clrn = (! aclr);
	usedw_is_1_dff.d = usedw_will_be_1;
	usedw_is_2_dff.clk = clock;
	usedw_is_2_dff.clrn = (! aclr);
	usedw_is_2_dff.d = usedw_will_be_2;
	wrreq_delaya[].clk = clock;
	wrreq_delaya[].clrn = (! aclr);
	wrreq_delaya[].d = ( ((! sclr) & valid_wreq), ((! sclr) & wrreq_delaya[1].q));
	IF (almost_full_comparer_dataa[] == almost_full_comparer_datab[]) THEN
		almost_full_comparer_aeb_int = VCC;
	ELSE
		almost_full_comparer_aeb_int = GND;
	END IF;
	almost_full_comparer_aeb = almost_full_comparer_aeb_int;
	almost_full_comparer_dataa[] = B"111111111";
	almost_full_comparer_datab[] = usedw_counter.q[];
	IF (three_comparison_dataa[] == three_comparison_datab[]) THEN
		three_comparison_aeb_int = VCC;
	ELSE
		three_comparison_aeb_int = GND;
	END IF;
	three_comparison_aeb = three_comparison_aeb_int;
	three_comparison_dataa[] = usedw_counter.q[];
	three_comparison_datab[] = B"000000011";
	rd_ptr_msb.aclr = aclr;
	rd_ptr_msb.clock = clock;
	rd_ptr_msb.cnt_en = (asynch_read_counter_enable & (! rd_ptr_lsb.q));
	rd_ptr_msb.sclr = sclr;
	usedw_counter.aclr = aclr;
	usedw_counter.clock = clock;
	usedw_counter.cnt_en = (valid_wreq $ valid_rreq);
	usedw_counter.sclr = sclr;
	usedw_counter.updown = valid_wreq;
	wr_ptr.aclr = aclr;
	wr_ptr.clock = clock;
	wr_ptr.cnt_en = valid_wreq;
	wr_ptr.sclr = sclr;
	asynch_read_counter_enable = pulse_ram_output;
	empty = empty_out;
	empty_out = (! empty_dff.q);
	full = full_out;
	full_out = full_dff.q;
	pulse_ram_output = ((((usedw_is_1 & wrreq_delaya[0].q) # ((usedw_is_2 & wrreq_delaya[1].q) & wrreq_delaya[0].q)) # ((! (usedw_is_1 # usedw_is_2)) & valid_rreq)) # ((usedw_is_2 & (! wrreq_delaya[1].q)) & valid_rreq));
	q[] = FIFOram.q_b[];
	ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].q) # (asynch_read_counter_enable & rd_ptr[]));
	rd_ptr[] = ( rd_ptr_msb.q[], (! rd_ptr_lsb.q));
	usedw[] = usedw_counter.q[];
	usedw_is_0 = (! usedw_is_0_dff.q);
	usedw_is_1 = usedw_is_1_dff.q;
	usedw_is_2 = usedw_is_2_dff.q;
	usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq)))))));
	usedw_will_be_1 = ((! sclr) & (((usedw_is_1 & (! (valid_wreq $ valid_rreq))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq))) # ((usedw_is_2 & valid_rreq) & (! valid_wreq))));
	usedw_will_be_2 = ((! sclr) & (((usedw_is_2_dff.q & (! (valid_wreq $ valid_rreq))) # ((usedw_is_1 & valid_wreq) & (! valid_rreq))) # ((three_comparison_aeb & valid_rreq) & (! valid_wreq))));
	valid_rreq = rreq;
	valid_wreq = wreq;
	wait_state = ((usedw_will_be_1 & (valid_wreq $ wrreq_delaya[1].q)) # ((usedw_will_be_2 & valid_wreq) & wrreq_delaya[1].q));
END;
--VALID FILE