library verilog;use verilog.vl_types.all;entity wb_conbus_arb is    generic(        grant0          : integer := 0;        grant1          : integer := 1;        grant2          : integer := 2;        grant3          : integer := 3;        grant4          : integer := 4;        grant5          : integer := 5;        grant6          : integer := 6;        grant7          : integer := 7    );    port(        clk             : in     vl_logic;        rst             : in     vl_logic;        req             : in     vl_logic_vector(7 downto 0);        gnt             : out    vl_logic_vector(2 downto 0)    );end wb_conbus_arb;