library verilog;use verilog.vl_types.all;entity wb_slv is    generic(        mem_size        : integer := 13    );    port(        clk             : in     vl_logic;        rst             : in     vl_logic;        adr             : in     vl_logic_vector(31 downto 0);        din             : in     vl_logic_vector(31 downto 0);        dout            : out    vl_logic_vector(31 downto 0);        cyc             : in     vl_logic;        stb             : in     vl_logic;        sel             : in     vl_logic_vector(3 downto 0);        we              : in     vl_logic;        ack             : out    vl_logic;        err             : out    vl_logic;        rty             : out    vl_logic    );end wb_slv;