?? zx.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity zx is
port (a :in std_logic_vector (7 downto 0);
b :out std_logic);
end zx;
architecture zx of zx is
begin
process (a)
begin
case a(7 downto 6) is
when "11" => b<='1';
when "00" => b<='0';
when "10" => b<='1';
when "01" => b<='0';
end case ;
end process;
end zx;
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