TimeQuest Timing Analyzer report for dds
Fri Nov 28 15:54:05 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Clocks
  4. Slow Model Fmax Summary
  5. Slow Model Setup Summary
  6. Slow Model Hold Summary
  7. Slow Model Recovery Summary
  8. Slow Model Removal Summary
  9. Slow Model Minimum Pulse Width
 10. Fast Model Setup Summary
 11. Fast Model Hold Summary
 12. Fast Model Recovery Summary
 13. Fast Model Removal Summary
 14. Fast Model Minimum Pulse Width
 15. Setup Transfers
 16. Hold Transfers
 17. Report TCCS
 18. Report RSKM
 19. Unconstrained Paths
 20. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                    ;
+--------------------+-------------------------------------------------+
; Quartus II Version ; Version 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name      ; dds                                             ;
; Device Family      ; Arria GX                                        ;
; Device Name        ; EP1AGX60DF780C6                                 ;
; Timing Models      ; Final                                           ;
; Delay Model        ; Combined                                        ;
; Rise/Fall Delays   ; Unavailable                                     ;
+--------------------+-------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                          ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+
; clk        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk } ;
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+


+--------------------------------------------------+
; Slow Model Fmax Summary                          ;
+------------+-----------------+------------+------+
; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------+------+
; 281.14 MHz ; 281.14 MHz      ; clk        ;      ;
+------------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------+
; Slow Model Setup Summary       ;
+-------+--------+---------------+
; Clock ; Slack  ; End Point TNS ;
+-------+--------+---------------+
; clk   ; -2.557 ; -221.865      ;
+-------+--------+---------------+


+-------------------------------+
; Slow Model Hold Summary       ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; clk   ; 0.796 ; 0.000         ;
+-------+-------+---------------+


-------------------------------
; Slow Model Recovery Summary ;
-------------------------------
No paths to report.


------------------------------
; Slow Model Removal Summary ;
------------------------------
No paths to report.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width                                                                                                                                                       ;
+--------+--------------+----------------+--------+-------+------------+---------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Pulse  ; Clock ; Clock Edge ; Target                                                                                                        ;
+--------+--------------+----------------+--------+-------+------------+---------------------------------------------------------------------------------------------------------------+
; -1.675 ; 1.000        ; 2.675          ; Period ; clk   ; Rise       ; clk                                                                                                           ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[0]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[0]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[1]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[1]                          ;