?? usb_new_vsc9_ram_xor_pkg.vhd
字號:
-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is usb_new.vhd
-- -----------------------------------------------------------------------------
-- Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
--
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips. This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
--
-- -----------------------------------------------------------------------------
-- USBFS22 Device Version 1.0
-- -----------------------------------------------------------------------------
-- usb_new/data/USBFS22/RTL/usb_new_vsc9_ram_xor_pkg.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr 3 17:23:42 2001
-- -----------------------------------------------------------------------------
-- HDLi Version 5.0 IP Bundle 2000.12.15
-- Top HDL file name is vsc9_ram.vhd
-- -----------------------------------------------------------------------------
-- Royal Philips Electronics
-- -----------------------------------------------------------------------------
-- Copyright 2001 by Royal Philips Electronics All rights reserved.
--
-- This module is property of Royal Philips Electronics (Philips) and its use
-- is granted to the customer for the sole purpose of implementing in silicon
-- provided by Philips. This module may only be used in accordance with the
-- provisions of the HDLi License Agreement.
--
-- -----------------------------------------------------------------------------
-- BIST SRAM Template Version 2.4
-- -----------------------------------------------------------------------------
-- vsc9_ram_xor_pkg.vhd : RTL VHDL
--
-- Compiled by arkrish on Tue Apr 3 11:53:35 2001
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package vsc9_ram_xor_pkg is
function vsc9_ram_Reduce_Xor (INPUT: Std_Logic_Vector) return Std_Logic;
end vsc9_ram_xor_pkg;
package body vsc9_ram_xor_pkg is
function vsc9_ram_Reduce_Xor (INPUT: Std_Logic_Vector) return Std_Logic is
variable RESULT : Std_Logic;
begin
RESULT := '0';
for j in INPUT'range loop
RESULT := INPUT(j) xor RESULT;
end loop;
return RESULT;
end;
end vsc9_ram_xor_pkg;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -