-------------------------------------------------------------------------- Create Date:     15:24:22 03/29/2006                               ---- Design Name:                                                       ---- Module Name:                                                       ---- Project Name:                                                      ---- Target Devices:  Architecture Independent                          ---- Tool versions:   ISE 8.1.03i                                       ---- Description:                                                       ----                                                                    ---- Dependencies:                                                      ----                                                                    ----                                                                    ---- Modification History:                                              ---------------------------------------------------------------------------- Date       By  Version   Change Description                        ---------------------------------------------------------------------------- 00-00-00   VL  0.1       Original                                  ---------------------------------------------------------------------------- DESCRIPTION-- A-law binary encoding table, S-sign-- Linear Input                   Segment   Quantization-- 12 11 10 9 8 7 6 5 4 3 2 1 0   7 6 5 4   3 2 1 0---- S  0  0  0 0 0 0 0 a b c d x   S 0 0 0   a b c d-- S  0  0  0 0 0 0 1 a b c d x   S 0 0 1   a b c d-- S  0  0  0 0 0 1 a b c d x x   S 0 1 0   a b c d-- S  0  0  0 0 1 a b c d x x x   S 0 1 1   a b c d-- S  0  0  0 1 a b c d x x x x   S 1 0 0   a b c d-- S  0  0  1 a b c d x x x x x   S 1 0 1   a b c d-- S  0  1  a b c d x x x x x x   S 1 1 0   a b c d-- S  1  a  b c d x x x x x x x   S 1 1 1   a b c dlibrary IEEE;use IEEE.std_logic_1164.ALL;use IEEE.std_logic_arith.ALL;use IEEE.std_logic_unsigned.ALL;entity alaw_enc_v1 isport(  clk       : in  std_logic;  reset_n   : in  std_logic;  data_in   : in  std_logic_vector (12 downto 1);  data_out  : out std_logic_vector (7 downto 0));end alaw_enc_v1;architecture behavioral of alaw_enc_v1 is  signal data_alaw    : std_logic_vector (6 downto 0);  signal data_in_rds  : std_logic_vector (6 downto 0);  signal sync_in_dff  : std_logic_vector (12 downto 1);  signal sync_out_dff : std_logic_vector (6 downto 0);begin-- Data Input SynchronisationSYNC_IN_PRC: process (clk, reset_n)begin  if reset_n = '0' then    sync_in_dff <= (others => '0');  elsif rising_edge(clk) then    sync_in_dff <= data_in;  end if;end process SYNC_IN_PRC;-- Data Conversiondata_in_rds <= sync_in_dff (11 downto 5);process (data_in_rds, sync_in_dff(10 downto 1))beginALAW_ENC_C1: case data_in_rds is  when "0000000" => data_alaw <= "000" & sync_in_dff(4 downto 1);  when "0000001" => data_alaw <= "001" & sync_in_dff(4 downto 1);  when "000001-" => data_alaw <= "010" & sync_in_dff(5 downto 2);  when "00001--" => data_alaw <= "011" & sync_in_dff(6 downto 3);  when "0001---" => data_alaw <= "100" & sync_in_dff(7 downto 4);  when "001----" => data_alaw <= "101" & sync_in_dff(8 downto 5);  when "01-----" => data_alaw <= "110" & sync_in_dff(9 downto 6);  when "1------" => data_alaw <= "111" & sync_in_dff(10 downto 7);  when others    => data_alaw <= (others => '0');end case ALAW_ENC_C1;end process;-- Data Output SynchronisationSYNC_OUT_PRC: process (clk, reset_n)begin  if reset_n = '0' then    sync_out_dff <= (others => '0');  elsif rising_edge(clk) then    sync_out_dff <= data_alaw;  end if;end process SYNC_OUT_PRC;data_out <= sync_in_dff(12) & sync_out_dff;end behavioral;