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-- Create Date:   10:50:37 03/18/2008
-- Design Name:   alaw_enc_v1
-- Module Name:   D:/Design_Projects/A_LAW/alaw_enc_v1_tb.vhd
-- Project Name:  alaw_enc_v1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: alaw_enc_v1
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.ALL;

entity alaw_enc_v1_tb_vhd is
  constant PERIOD : time := 10 ns;
end alaw_enc_v1_tb_vhd;

architecture behavior of alaw_enc_v1_tb_vhd is

-- component declaration for the unit under test (uut)
	component alaw_enc_v1
	port(
  clk       : in  std_logic;
  reset_n   : in  std_logic;
  data_in   : in  std_logic_vector (12 downto 1);
  data_out  : out std_logic_vector (7 downto 0)
		);
	end component;

	--inputs
	signal data_in :  std_logic_vector(12 downto 1) := (others=>'0');
	signal tb_clock   :  std_logic := '0';
	signal tb_resetn  :  std_logic := '0';
	signal tb_cnt     :  std_logic_vector(12 downto 1);

	--outputs
	signal data_out :  std_logic_vector(7 downto 0);

begin

TB_CNT_PRC: process (tb_clock, tb_resetn)
begin
  if (tb_resetn = '0') then
    tb_cnt <= (others => '0');
  elsif rising_edge (tb_clock) then
    tb_cnt <= tb_cnt + '1';
  end if;
end process TB_CNT_PRC;


	-- instantiate the unit under test (uut)
	uut: alaw_enc_v1 port map(
		clk     => tb_clock,
    reset_n => tb_resetn,
    data_in => tb_cnt,
		data_out => data_out
	);

tb_resetn <= '1' after 50 ns;
tb_clock <= NOT(tb_clock) after PERIOD/2;


end;