JDF F
// Created by Project Navigator ver 1.0
PROJECT spi_master
DESIGN spi_master Normal
DEVFAM xpla3
DEVFAMTIME 1039647829
DEVICE xcr3256xl
DEVICETIME 1039647829
DEVPKG TQ144
DEVPKGTIME 0
DEVSPEED -7
DEVSPEEDTIME 0
FLOW XST VHDL
FLOWTIME 0
MODULE sck_logic.vhd
MODSTYLE sck_logic Normal
MODULE upcnt5.vhd
MODSTYLE upcnt5 Normal
MODULE upcnt4.vhd
MODSTYLE upcnt4 Normal
MODULE spi_master.vhd
MODSTYLE spi_master Normal
MODULE spi_interface.vhd
MODSTYLE spi_interface Normal
MODULE spi_xmit_shift_reg.vhd
MODSTYLE spi_xmit_shift_reg Normal
MODULE spi_control_sm.vhd
MODSTYLE spi_control_sm Normal
MODULE spi_rcv_shift_reg.vhd
MODSTYLE spi_rcv_shift_reg Normal
MODULE uc_interface.vhd
MODSTYLE uc_interface Normal
[Normal]
xcpldFitDesInReg=xstvhd, xpla3, Implementation.t_vm6File, 1039218774, False
[STATUS-ALL]
spi_master.ngcFile=WARNINGS,1039647865
spi_master.postParVHDLSimModel=WARNINGS,1039647865
[STRATEGY-LIST]
Normal=True