; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 46        ;
; Total combinational functions   ; 40        ;
;     -- Total 4-input functions  ; 23        ;
;     -- Total 3-input functions  ; 6         ;
;     -- Total 2-input functions  ; 10        ;
;     -- Total 1-input functions  ; 1         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 18        ;
; I/O pins                        ; 27        ;
; Maximum fan-out node            ; count2[1] ;
; Maximum fan-out                 ; 21        ;
; Total fan-out                   ; 178       ;
; Average fan-out                 ; 2.44      ;
+---------------------------------+-----------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
; |divider                   ; 46 (46)     ; 18           ; 0           ; 27   ; 28 (28)      ; 6 (6)             ; 12 (12)          ; 0 (0)           ; |divider            ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 18    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |divider ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type                                           ;
+----------------+-------+------------------------------------------------+
; k              ; 3     ; Integer                                        ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/workroom/產(chǎn)品/開放式CPU實(shí)驗(yàn)教學(xué)系統(tǒng)TEC-CA/TEC-CA出廠光盤/實(shí)驗(yàn)/7-divider/divider.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Aug 23 16:25:42 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off divider -c divider
Info: Found 2 design units, including 1 entities, in source file divider.vhd
    Info: Found design unit 1: divider-structural
    Info: Found entity 1: divider
Info: Elaborating entity "divider" for the top level hierarchy
Warning: VHDL Process Statement warning at divider.vhd(123): signal "remainder" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at divider.vhd(138): signal "remainder" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at divider.vhd(139): signal "remainder" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: One or more bidirs are fed by always enabled tri-state buffers
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "remainder[0]" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "finish" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "remainder[1]" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "remainder[2]" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "remainder[3]" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "remainder[5]" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "remainder[6]" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "remainder[7]" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "remainder[4]" is moved to its source
    Info: Fanout of permanently enabled tri-state buffer feeding bidir "remainder[8]" is moved to its source
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "remainder[0]~45"
    Warning: Node "remainder[1]~46"
    Warning: Node "remainder[2]~47"
    Warning: Node "remainder[3]~48"
    Warning: Node "remainder[4]~49"
    Warning: Node "remainder[5]~50"
    Warning: Node "remainder[6]~51"
    Warning: Node "remainder[7]~52"
    Warning: Node "remainder[8]~53"
    Warning: Node "finish~1"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "remainder_r[3]" stuck at GND
Info: Implemented 73 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 8 output pins
    Info: Implemented 10 bidirectional pins
    Info: Implemented 46 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
    Info: Processing ended: Tue Aug 23 16:25:45 2005
    Info: Elapsed time: 00:00:04