//------------------------------------------------------------------------------
//
// File : ct_burst_r_w_ws.tf
// Last Modification: 06/26/2001
//
// Created In SpDE Version: SpDE 8.22
// Author :	Richard Yuan, QuickLogic Corporation
// Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	This file implements the master burst read/write with wait states tests of the
//	PCI compliance test suite to test the QL5332-33/QL5432-33 devices in their
//	reference designs.
//	 
// Hierarchy:
//	This file is to be included by ct_master.tf.
//
// History:	
//	Date	        Author					Version
//	06/26/01		Richard Yuan			1.0
//		- Header added to conform to coding standard.
//
//------------------------------------------------------------------------------


	// enable bus master and clear status bits
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h4,64'hFFFF0156,CONFIG_WRITE,8'hFF,0,0,1,1,1,0); 
	// write test pattern to lower memory in Target
	master_2.data_array[0] = 32'hABCDEFAB;
	master_2.data_array[1] = 32'hCDEFABCD;
	master_2.data_array[2] = 32'hEFABCDEF;
	master_2.data_array[3] = 32'h01234567;
	master_2.data_array[4] = 32'h89012345;
	master_2.data_array[5] = 32'h67890123;
	for (i = 0; i < 6; i = i + 1) begin
		master_2.be_array[i] = 4'hF;
		end
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h11110000,64'h0,MEM_WRITE,8'hFF,0,0,6,1,1,0); 
	// clear upper memory in target
	master_2.data_array[0] = 32'h00000000;
	master_2.data_array[1] = 32'h00000000;
	master_2.data_array[2] = 32'h00000000;
	master_2.data_array[3] = 32'h00000000;
	master_2.data_array[4] = 32'h00000000;
	master_2.data_array[5] = 32'h00000000;
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h11118000,64'h0,MEM_WRITE,8'hFF,0,0,6,1,1,0); 
	// Configure and enable a 1 cycle DMA read from the Target
	master_2.data_array[0] = 32'h00060006;
	master_2.data_array[1] = 32'h11118000 >> 2;
	master_2.data_array[2] = 32'h11110000 >> 2;

	if (mrl) master_2.data_array[3] = {8'b11_1111_01,24'h000000};
	else if (mrm) master_2.data_array[3] = {8'b11_1110_01,24'h000000};
	else master_2.data_array[3] = 32'hC1000000;

	repeat (5) @(posedge CLK);
	master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,0,0,4,1,1,0); 
	//Wait for Master DMA to complete
	for (i = 0; i < 20; i = i + 1) begin
		repeat (20) @(posedge CLK);
		master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
		if (master_2.data_read[25:24] == 2'b00) begin
			$display("\tMaster DMA Completed Successfully");
			i = 300;
			end
		if (master_2.data_read[25:24] == 2'b10) begin
			$display("\tMaster DMA did not complete");
			i = 300;
			end
		end
	if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout)");
	repeat (5) @(posedge CLK);

	if (mrl | mrm) master_2.target_access(32'h2200010C,{16'hC000,8'b00_0_111_01,8'h00},MEM_WRITE,8'hFF,0,0,1,1,1,0);
	else master_2.target_access(32'h2200010C,64'hC0000100,MEM_WRITE,8'hFF,0,0,1,1,1,0);

	//Wait for Master DMA to complete
	for (i = 0; i < 20; i = i + 1) begin
		repeat (20) @(posedge CLK);
		master_2.target_access(32'h2200010C,64'h0,MEM_READ,8'hFF,1'b0,1'b0,7'h01,4'h1,4'h1,1'b0);
		if (master_2.data_read[9:8] == 2'b00) begin
			$display("\tMaster DMA Completed Successfully");
			i = 300;
			end
		if (master_2.data_read[9:8] == 2'b10) begin
			$display("\tMaster DMA did not complete");
			i = 300;
			end
		end
	if (i < 300) $display("\tMaster DMA did not complete (DMA Timeout)");
	$display("\tComparing Data at Target Location 0 with Target Location 0x8000");
	// read test pattern from upper memory in Target and compare with expected
	master_2.data_array[0] = 32'hABCDEFAB;
	master_2.data_array[1] = 32'hCDEFABCD;
	master_2.data_array[2] = 32'hEFABCDEF;
	master_2.data_array[3] = 32'h01234567;
	master_2.data_array[4] = 32'h89012345;
	master_2.data_array[5] = 32'h67890123;
	repeat (5) @(posedge CLK);
	master_2.target_access_pf(32'h11118000,32'hABCDEFAB,MEM_READ_MULT,8'hFF,0,0,6,1,1,0, pass, 0);