`timescale 1ns/1ns

/************************************************************************
** File : r128x32_25um.tf
** Design Date: June 9, 1998
** Creation Date : Fri Apr 05 15:22:04 2002

** Created By SpDE Version : SpDE 9.3 Dev Build2
** Author: Robert Maul, QuickLogic Corporation,
** Copyright (C) 1998, Customers of QuickLogic may copy and modify this
** file for use in designing QuickLogic devices only.
** Description: This is a sample test fixture for your RAM bank.
** For each address, data is loaded in then read back
** The data is the address of the RAM location.
** The intended use of this file is to help users verify that the
** RAM Bank that is generated by SpDE is functionally correct.
************************************************************************/

module t;

integer i;

reg wclk, rclk, we, re;
reg [6:0] wa;
reg [6:0] ra;
reg  [31:0] wd;
wire [31:0] rd;

 r128x32_25um m(.wa(wa),.ra(ra),.wd(wd),.rd(rd),.we(we),.re(re),.wclk(wclk),.rclk(rclk));

always
#10 wclk = ~wclk;
always
#10 rclk = ~rclk;

initial
begin
  wclk = 0;
  we = 1;
  rclk = 0;
  re = 1;
  i = 0;
  repeat(128)
    begin
        wa = i;
        wd = i;
        #20 i=i+1;
    end
  i = 0;
  we = 0;
  repeat(128)
    begin
        ra = i;
        #20 i=i+1;
    end
 $stop;
 $finish;
end

endmodule;