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# File name : pci5632_280aldec_post.do
# Active HDL macro script 
# to perform post layout simulation
####################################################################

set macropath d:\pasic\spde\data
#set curpath c:\pasic\design\reference\pci5632_280\verilog
set curpath d:\project\CardBus\Source\verilog
set primitivepath d:\pasic\spde\data\Ql5632-33\pci32_25um
set design_name cardbus_5632post
set adf_file_name cardbus_5632post.adf
set sdf_file $curpath/cardbus_5632.sdf

createdesign $design_name $curpath
opendesign $adf_file_name

alib work
set worklib work

addfile -c -txt $curpath/bus_chk.mem

addfile -verilog $macropath/qlprim.v
alog $macropath/qlprim.v

#addfile -verilog $primitivepath/V1_2/pci3233_25um.v
#alog $primitivepath/V1_2/pci3233_25um.v

addfile -verilog $curpath/cardbus_5632.vq
alog $curpath/cardbus_5632.vq

addfile -verilog $curpath/cardbus_5632.tf
alog $curpath/cardbus_5632.tf

addfile -sdf $sdf_file
asim -sdfmax m=$sdf_file -t ps t

view wave

wave /t/PERRN
wave /t/SERRN
wave /t/PAR
wave /t/REQN
wave /t/GNTN
wave /t/RSTN
wave /t/CLK
wave /t/IDSEL
wave -literal -hex /t/AD
wave -literal -hex /t/CBEN
wave /t/FRAMEN
wave /t/IRDYN
wave /t/DEVSELN
wave /t/TRDYN
wave /t/STOPN

run -all
#write mem pci5632_280aldec_post.log
#endsim