//------------------------------------------------------------------------------
//
// File : pci_cmd_test.tf
// Last Modification: 06/26/2001
//
// Created In SpDE Version: SpDE 8.22
// Author :	Richard Yuan, QuickLogic Corporation
// Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
// this file for use in designing with QuickLogic devices only.
//	
// Description :
//	This file tests the capability of QL5332-33/QL5432-33 devices to generate
//	all kinds of PCI transactions.
//	 
// Hierarchy:
//	This file is to be included by pci5(3/4)32_208.tf.
//
// History:	
//	Date	        Author					Version
//	06/26/01		Richard Yuan			1.0
//		- Header added to conform to coding standard.
//
//------------------------------------------------------------------------------


// PCI Command Test
// this test takes about 50us of simulation time

// set up the simulation target wait state response
target_1.WAITSTATES_ENABLE = 1;    //Enable insertion of wait states
target_1.VARIABLE_WAITS = 1;       //Enable variable wait lengths (1 or 0)
target_1.MAX_WAITS = 5;            //Max # of wait states inserted in variable waits mode
target_1.MIN_WAITS = 0;            //Min # of wait states inserted in variable waits mode
target_1.INITIAL_WAITS = 1;        //# of waits to insert before first trdy
target_1.SUBSEQUENT_WAITS = 1;     //# of waits to insert before subsequent trdy's
target_1.STOP_ENABLE = 1;
target_1.STOP_COUNT = 3;

// write 3 dwords to configuration space to set up the master
// Set the MWI enable bit
master_2.data_array[0] = 32'h00000156;
master_2.data_array[1] = 32'h00000000;
master_2.data_array[2] = 32'h00004000;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h4,32'h0,CONFIG_WRITE,8'hFF,1'b0,1'b0,3,1,1,1'b0); 



$display("\tStart of various PCI command test, %d\n",$time);

$display("\tInterrupt Acknowledge, %d",$time);
// set up Interrupt Acknowledge cycle
// the simulation target should respond with data 0x78787878
CurRxSize = 1;	// master write
CurTxSize = CurRxSize;	// master read
// master read command 3'b000, all byte lanes on, store data in master data reg (not FIFO)
DMACtrlReg = {8'b01_1000_01,8'b0,8'b0,8'b10_000000};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = CurRxAddr;
master_2.data_array[2] = CurTxAddr;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
repeat (30) @(posedge CLK);

master_2.target_access(32'h4,64'h0,CONFIG_READ,8'hFF,0,0,1,1,1,0);
if (master_2.data_read[29] == 1) begin
	$display("\t\tMaster Abort Status Bit Set ... Failed");
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h4,64'hFFFF0156,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
	end
else $display("\t\tMaster Abort Status Bit Not Set ... Passed"); 

$display("\tComparing data read with 0x78787878");
repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h2200011C,32'h78787878,MEM_READ,8'hFF,0,0,1,1,1,0, pass, 0); 



$display("\tSpecial Cycle (with customized byte enable of 4'b1100), %d",$time);
$display("\tMaster Abort expected, but Master Abort Status bit expected unset");
// set up Special Cycle
// the simulation target should save data and store at offset 0x0 in its BAR0
// Write to master data reg for master write data (16'h0001 is halt)
repeat (5) @(posedge CLK);
master_2.target_access(32'h2200011C,64'h00000001,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0); 

CurRxSize = 1;	// master write
CurTxSize = CurRxSize;	// master read
// master write command is 3'b000, only lower two byte lanes on
DMACtrlReg = {8'h40,8'b000000_11,8'b00_0_011_01,8'b01_000000};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = CurRxAddr;
master_2.data_array[2] = CurTxAddr;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
repeat (30) @(posedge CLK);

master_2.target_access(32'h4,64'h0,CONFIG_READ,8'hFF,0,0,1,1,1,0);
if (master_2.data_read[29] == 1) begin
	$display("\t\tMaster Abort Status Bit Set ... Failed");
	repeat (5) @(posedge CLK);
	master_2.target_access(32'h4,64'hFFFF0156,CONFIG_WRITE,8'hFF,0,0,1,1,1,0);
	end
else $display("\t\tMaster Abort Status Bit Not Set ... Passed"); 

$display("\tComparing data read with 0x0001");
repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h11110000,32'h00000001,MEM_READ,8'hF3,0,0,1,1,1,0, pass, 0); 
repeat (5) @(posedge CLK);
master_2.target_access(32'h11110000,32'h80018001,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0); 



$display("\tConfiguration Write, %d",$time);
$display("\tWrite 0xEDEDEDED to BAR 0 (offset 0x10) of PCI configuration target");
$display("\tIDSEL of the PCI configuration target is tied to AD[30]");
// Config Write
// Write to master data reg for master write data
repeat (5) @(posedge CLK);
master_2.target_access(32'h2200011C,64'hEDEDEDED,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0); 

CurRxSize = 1;	// master write
CurTxSize = CurRxSize;	// master read
// master write command 3'b101, all byte lanes on
DMACtrlReg = {8'h40,8'b000000_00,8'b00_0_101_01,8'b01_000000};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = 32'h40000010 >> 2;
master_2.data_array[2] = CurTxAddr;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
repeat (30) @(posedge CLK);



$display("\tConfiguration Read, %d",$time);
$display("\tRead from BAR 0 (offset 0x10) of the PCI configuration target");
// Configuration Read
CurRxSize = 1;	// master write
CurTxSize = CurRxSize;	// master read
// master read command 3'b101, all byte lanes on, store data in master data reg
DMACtrlReg = {8'b01_1101_01,8'b0,8'b0,8'b10_000000};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = CurRxAddr;
master_2.data_array[2] = 32'h40000010 >> 2;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
repeat (30) @(posedge CLK);

$display("\tComparing data read with 0xEDEDEDED");
repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h2200011C,32'hEDEDEDED,MEM_READ,8'hFF,0,0,1,1,1,0, pass, 0); 



$display("\tI/O Write (with customized byte enable of 4'b1110, %d",$time);
$display("\tWrite 0x07 to PCI I/O target BAR 0 offset 0x04");
// I/O Write
// Write to master data reg for master write data
repeat (5) @(posedge CLK);
master_2.target_access(32'h2200011C,64'h00000007,MEM_WRITE,8'hFF,1'b0,1'b0,1,1,1,1'b0); 

CurRxSize = 1;	// master write
CurTxSize = CurRxSize;	// master read
// master write command 3'b001, only lowest byte lane on
DMACtrlReg = {8'h40,8'b000000_11,8'b10_0_001_01,8'b01_000000};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = 32'h01110004 >> 2;
master_2.data_array[2] = CurTxAddr;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
repeat (30) @(posedge CLK);



$display("\tI/O Read, %d",$time);
$display("\tRead from PCI I/O target BAR 0 offset 0x04");
// I/O Read
CurRxSize = 1;	// master write
CurTxSize = CurRxSize;	// master read
// master read command 3'b001, only lowest byte lane on, store data in master data reg
DMACtrlReg = {8'b01_1001_01,8'b00_1110_00,8'b0,8'b10_000000};
DMARxTxCntReg = {CurTxSize, CurRxSize};

// write the DMA setup data to the DMA control registers in the master
master_2.data_array[0] = DMARxTxCntReg;
master_2.data_array[1] = CurRxAddr;
master_2.data_array[2] = 32'h01110004 >> 2;
master_2.data_array[3] = DMACtrlReg;
master_2.be_array[0] = 8'hFF;
master_2.be_array[1] = 8'hFF;
master_2.be_array[2] = 8'hFF;
master_2.be_array[3] = 8'hFF;

repeat (5) @(posedge CLK);
master_2.target_access(32'h22000100,64'h0,MEM_WRITE,8'hFF,1'b0,1'b0,4,1,1,1'b0); 
repeat (30) @(posedge CLK);

$display("\tComparing data read with 0x07");
repeat (5) @(posedge CLK);
master_2.target_access_pf(32'h2200011C,32'h00000007,MEM_READ,8'hF1,0,0,1,1,1,0, pass, 0);