?? ten.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ten is
port(reset,clk :in std_logic;
q :out std_logic_vector(3 downto 0));
end ten;
architecture tenx of ten is
signal qo:std_logic_vector(3 downto 0);
begin
process(clk,reset,qo)
begin
if reset='0' then
qo<="0000";
else if(clk'event and clk='1') then
if qo<"1001" then
qo<=qo+1;
else
qo<="0000";
end if;
end if;
end if;
q<=qo;
end process;
end tenx;
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