?? sel_7.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
entity sel_7 is
port(d :in std_logic_vector(6 downto 0);
y :out std_logic);
end sel_7;
architecture sel_7x of sel_7 is
begin
process(d)
variable temp:integer;
begin
temp:=0;
for i in 0 to 6 loop
if(d(i)='1') then
temp:=temp+1;
end if;
end loop;
if(temp>3) then
y<='1';
else
y<='0';
end if;
end process;
end sel_7x;
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