?? lichengji0.rpt
字號:
- 1 - B 04 DFFE + 0 2 1 0 :4
- 3 - B 04 DFFE + 1 2 1 1 shifen3 (:10)
- 8 - B 04 DFFE + 1 2 1 3 shifen2 (:11)
- 5 - B 04 DFFE + 1 2 1 3 shifen1 (:12)
- 7 - B 04 DFFE + 1 0 1 4 shifen0 (:13)
- 2 - B 04 OR2 ! 0 4 0 4 :75
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\kechengsheji\lichengji0.rpt
lichengji0
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 3/ 96( 3%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\kechengsheji\lichengji0.rpt
lichengji0
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
Device-Specific Information: f:\kechengsheji\lichengji0.rpt
lichengji0
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 reset
Device-Specific Information: f:\kechengsheji\lichengji0.rpt
lichengji0
** EQUATIONS **
clk : INPUT;
reset : INPUT;
stop : INPUT;
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC1_B4;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC1_B12, type is buried.
-- synthesized logic cell
!_LC1_B12 = _LC1_B12~NOT;
_LC1_B12~NOT = LCELL(!reset);
-- Node name is ':13' = 'shifen0'
-- Equation name is 'shifen0', location is LC7_B4, type is buried.
shifen0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ001 = !shifen0 & !stop
# shifen0 & stop;
-- Node name is ':12' = 'shifen1'
-- Equation name is 'shifen1', location is LC5_B4, type is buried.
shifen1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ002 = !_LC2_B4 & !shifen0 & shifen1
# !_LC2_B4 & shifen0 & !shifen1 & !stop
# shifen1 & stop;
-- Node name is ':11' = 'shifen2'
-- Equation name is 'shifen2', location is LC8_B4, type is buried.
shifen2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ003 = !_LC2_B4 & _LC4_B4 & !stop
# shifen2 & stop;
-- Node name is ':10' = 'shifen3'
-- Equation name is 'shifen3', location is LC3_B4, type is buried.
shifen3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!reset), VCC, VCC);
_EQ004 = !_LC2_B4 & !_LC6_B4 & shifen3
# !_LC2_B4 & _LC6_B4 & !shifen3 & !stop
# shifen3 & stop;
-- Node name is 'shifen_10'
-- Equation name is 'shifen_10', type is output
shifen_10 = shifen0;
-- Node name is 'shifen_11'
-- Equation name is 'shifen_11', type is output
shifen_11 = shifen1;
-- Node name is 'shifen_12'
-- Equation name is 'shifen_12', type is output
shifen_12 = shifen2;
-- Node name is 'shifen_13'
-- Equation name is 'shifen_13', type is output
shifen_13 = shifen3;
-- Node name is '|LPM_ADD_SUB:66|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = LCELL( _EQ005);
_EQ005 = shifen0 & shifen1 & shifen2;
-- Node name is '|LPM_ADD_SUB:66|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = LCELL( _EQ006);
_EQ006 = !shifen1 & shifen2
# !shifen0 & shifen2
# shifen0 & shifen1 & !shifen2;
-- Node name is ':4'
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = DFFE( _LC2_B4, GLOBAL( clk), VCC, VCC, !_LC1_B12);
-- Node name is ':75'
-- Equation name is '_LC2_B4', type is buried
!_LC2_B4 = _LC2_B4~NOT;
_LC2_B4~NOT = LCELL( _EQ007);
_EQ007 = shifen2
# shifen1
# !shifen3
# !shifen0;
Project Information f:\kechengsheji\lichengji0.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,144K
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -