library ieee;
use ieee.std_logic_1164.all;
entity lx38 is
      port(a,b,c      :in std_logic;
           g1,g2a,g2b :in std_logic;
           l          :out std_logic_vector(7 downto 0));
end lx38;
architecture lx38_x of lx38 is
       signal dizhi:std_logic_vector(2 downto 0);
begin
       dizhi<=c&b&a;
       process(dizhi,g1,g2a,g2b)
       begin
            if(g1='1'and g2a='0' and g2b='0') then
                  case dizhi is
                       when "000" =>l<="11111110";
                       when "001" =>l<="11111101";
                       when "010" =>l<="11111011";
                       when "011" =>l<="11110111";
                       when "100" =>l<="11101111";
                       when "101" =>l<="11011111";
                       when "110" =>l<="10111111";
                       when "111" =>l<="01111111";
                       when others =>l<="11111111";
                 end case;
            else
                   l<="11111111";
            end if;
       end process;
 end lx38_x;