library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xiaosh is
  port(clk,reset,en,stop     :in std_logic;
        able                 :in std_logic;   
       co                    :out std_logic;
       shifen_1,baifen_0     :out std_logic_vector(3 downto 0));
end xiaosh;
architecture cnt_100_x of xiaosh is
signal shifen,baifen:std_logic_vector(3 downto 0);
 begin
    process(clk,reset,en,stop,able)
          
    begin
        if(reset='1' ) then
          shifen<="0000";baifen<="0000";
        else if(  clk'event and clk='1') then
             if(en='1') then
               baifen<=baifen+1;
               shifen<=shifen+1;
               if (baifen=9 and shifen=9) then baifen<="0000";shifen<="0000";co<='1';
                else co<='0';
               end if;
               if(able='1') then 
                    baifen<=baifen+1;shifen<=shifen+1;
                    if (baifen=9 and shifen=9) then 
                           co<='1';
                       else co<='0';
                     end if;
                        if(baifen>8 and shifen>8) then
                           baifen<="0000";shifen<="0000";
                        end if;
               end if;                    
               end if;
                          
             if(stop='1') then
               shifen<=shifen;
               baifen<=baifen;
             end if;      
            end if;
        end if; 
        shifen_1<=shifen;
       baifen_0<=baifen;
  end process;
end cnt_100_x;