?? control.rpt
字號:
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 1/ 48( 2%) 1/ 48( 2%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\mux\kechengsheji\control.rpt
control
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 clk
Device-Specific Information: d:\mux\kechengsheji\control.rpt
control
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 13 start
Device-Specific Information: d:\mux\kechengsheji\control.rpt
control
** EQUATIONS **
clk : INPUT;
reset : INPUT;
speed1 : INPUT;
speed2 : INPUT;
speed3 : INPUT;
start : INPUT;
stop : INPUT;
-- Node name is 'clk_out'
-- Equation name is 'clk_out', type is output
clk_out = _LC1_A10;
-- Node name is ':21' = 'q0'
-- Equation name is 'q0', location is LC5_A10, type is buried.
q0 = DFFE(!q0, GLOBAL( clk), VCC, VCC, start);
-- Node name is ':20' = 'q1'
-- Equation name is 'q1', location is LC4_A10, type is buried.
q1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, start);
_EQ001 = q0 & !q1
# !q0 & q1;
-- Node name is ':19' = 'q2'
-- Equation name is 'q2', location is LC1_A11, type is buried.
q2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, start);
_EQ002 = !_LC8_A10 & q2
# _LC8_A10 & !q2;
-- Node name is ':18' = 'q3'
-- Equation name is 'q3', location is LC1_A3, type is buried.
q3 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, start);
_EQ003 = !q2 & q3
# !_LC8_A10 & q3
# _LC8_A10 & q2 & !q3;
-- Node name is ':17' = 'q4'
-- Equation name is 'q4', location is LC2_A3, type is buried.
q4 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, start);
_EQ004 = !_LC2_A11 & q4
# !q3 & q4
# _LC2_A11 & q3 & !q4;
-- Node name is ':16' = 'q5'
-- Equation name is 'q5', location is LC4_A3, type is buried.
q5 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, start);
_EQ005 = !_LC3_A3 & q5
# _LC3_A3 & !q5;
-- Node name is ':15' = 'q6'
-- Equation name is 'q6', location is LC5_A3, type is buried.
q6 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, start);
_EQ006 = !q5 & q6
# !_LC3_A3 & q6
# _LC3_A3 & q5 & !q6;
-- Node name is ':14' = 'q7'
-- Equation name is 'q7', location is LC7_A3, type is buried.
q7 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, start);
_EQ007 = !_LC6_A3 & q7
# !q6 & q7
# _LC6_A3 & q6 & !q7;
-- Node name is ':13' = 'q8'
-- Equation name is 'q8', location is LC2_A10, type is buried.
q8 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, start);
_EQ008 = !_LC8_A3 & q8
# _LC8_A3 & !q8;
-- Node name is ':12' = 'q9'
-- Equation name is 'q9', location is LC3_A10, type is buried.
q9 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, start);
_EQ009 = !q8 & q9
# !_LC8_A3 & q9
# _LC8_A3 & q8 & !q9;
-- Node name is 're'
-- Equation name is 're', type is output
re = _LC1_C21;
-- Node name is 'stop_1'
-- Equation name is 'stop_1', type is output
stop_1 = _LC3_C3;
-- Node name is '|LPM_ADD_SUB:81|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A10', type is buried
_LC8_A10 = LCELL( _EQ010);
_EQ010 = q0 & q1;
-- Node name is '|LPM_ADD_SUB:81|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A11', type is buried
_LC2_A11 = LCELL( _EQ011);
_EQ011 = _LC8_A10 & q2;
-- Node name is '|LPM_ADD_SUB:81|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A3', type is buried
_LC3_A3 = LCELL( _EQ012);
_EQ012 = _LC8_A10 & q2 & q3 & q4;
-- Node name is '|LPM_ADD_SUB:81|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A3', type is buried
_LC6_A3 = LCELL( _EQ013);
_EQ013 = _LC3_A3 & q5;
-- Node name is '|LPM_ADD_SUB:81|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A3', type is buried
_LC8_A3 = LCELL( _EQ014);
_EQ014 = _LC3_A3 & q5 & q6 & q7;
-- Node name is ':8'
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = DFFE( _EQ015, GLOBAL( clk), GLOBAL( start), VCC, VCC);
_EQ015 = _LC7_A10 & !speed1
# q0 & speed1;
-- Node name is ':256'
-- Equation name is '_LC6_A10', type is buried
_LC6_A10 = LCELL( _EQ016);
_EQ016 = q9 & speed3
# _LC1_A10 & !speed3;
-- Node name is ':269'
-- Equation name is '_LC7_A10', type is buried
_LC7_A10 = LCELL( _EQ017);
_EQ017 = _LC6_A10 & !speed2
# q1 & speed2;
-- Node name is ':437'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = LCELL( _EQ018);
_EQ018 = reset & start;
-- Node name is ':443'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = LCELL( _EQ019);
_EQ019 = start & stop;
Project Information d:\mux\kechengsheji\control.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,413K
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