?? bufu1.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bufu1 is
port(clk,reset,stop :in std_logic;
co :out std_logic);
end bufu1;
architecture cnt_100_x of bufu1 is
signal shi,bai:std_logic_vector(3 downto 0);
begin
process(reset,clk,stop)
begin
if(reset='1' ) then
shi<="0000";bai<="0000";
else if(clk'event and clk='1') then
if(shi=9) then shi<="0000";
if (bai=9) then bai<="0000";
else bai<=bai+1;
end if;
else shi<=shi+1;
end if;
if(shi=9 and bai=9) then
co<='1';
else
co<='0';
end if;
end if;
end if;
if(stop='1') then
shi<=shi;
bai<=bai;
end if;
end process;
end cnt_100_x;
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