-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--A1L37Q is seg[0]~reg0
--operation mode is normal

A1L37Q_lut_out = hex[2] & !hex[1] & (hex[0] $ !hex[3]) # !hex[2] & hex[0] & (hex[1] $ !hex[3]);
A1L37Q = DFFE(A1L37Q_lut_out, clk_div, , , );


--A1L57Q is seg[1]~reg0
--operation mode is normal

A1L57Q_lut_out = hex[1] & (hex[0] & (hex[3]) # !hex[0] & hex[2]) # !hex[1] & hex[2] & (hex[0] $ hex[3]);
A1L57Q = DFFE(A1L57Q_lut_out, clk_div, , , );


--A1L77Q is seg[2]~reg0
--operation mode is normal

A1L77Q_lut_out = hex[2] & hex[3] & (hex[1] # !hex[0]) # !hex[2] & !hex[0] & hex[1] & !hex[3];
A1L77Q = DFFE(A1L77Q_lut_out, clk_div, , , );


--A1L97Q is seg[3]~reg0
--operation mode is normal

A1L97Q_lut_out = hex[1] & (hex[0] & hex[2] # !hex[0] & !hex[2] & hex[3]) # !hex[1] & !hex[3] & (hex[0] $ hex[2]);
A1L97Q = DFFE(A1L97Q_lut_out, clk_div, , , );


--A1L18Q is seg[4]~reg0
--operation mode is normal

A1L18Q_lut_out = hex[1] & hex[0] & (!hex[3]) # !hex[1] & (hex[2] & (!hex[3]) # !hex[2] & hex[0]);
A1L18Q = DFFE(A1L18Q_lut_out, clk_div, , , );


--A1L38Q is seg[5]~reg0
--operation mode is normal

A1L38Q_lut_out = hex[0] & (hex[3] $ (hex[1] # !hex[2])) # !hex[0] & hex[1] & !hex[2] & !hex[3];
A1L38Q = DFFE(A1L38Q_lut_out, clk_div, , , );


--A1L58Q is seg[6]~reg0
--operation mode is normal

A1L58Q_lut_out = hex[0] & !hex[3] & (hex[1] $ !hex[2]) # !hex[0] & !hex[1] & (hex[2] $ !hex[3]);
A1L58Q = DFFE(A1L58Q_lut_out, clk_div, , , );


--hex[0] is hex[0]
--operation mode is arithmetic

hex[0]_lut_out = udreg $ hex[0] $ A1L56;
hex[0] = DFFE(hex[0]_lut_out, clk_div, , , );

--A1L36 is hex[0]~38
--operation mode is arithmetic

A1L36 = CARRY(udreg & !hex[0] & !A1L56 # !udreg & (!A1L56 # !hex[0]));


--hex[1] is hex[1]
--operation mode is arithmetic

hex[1]_lut_out = udreg $ hex[1] $ A1L36;
hex[1] = DFFE(hex[1]_lut_out, clk_div, , , );

--A1L76 is hex[1]~41
--operation mode is arithmetic

A1L76 = CARRY(udreg & hex[1] & !A1L36 # !udreg & (hex[1] # !A1L36));


--hex[2] is hex[2]
--operation mode is arithmetic

hex[2]_lut_out = udreg $ hex[2] $ !A1L76;
hex[2] = DFFE(hex[2]_lut_out, clk_div, , , );

--A1L96 is hex[2]~44
--operation mode is arithmetic

A1L96 = CARRY(udreg & (!A1L76 # !hex[2]) # !udreg & !hex[2] & !A1L76);


--hex[3] is hex[3]
--operation mode is normal

hex[3]_lut_out = udreg $ hex[3] $ A1L96;
hex[3] = DFFE(hex[3]_lut_out, clk_div, , , );


--clk_div is clk_div
--operation mode is normal

clk_div_lut_out = A1L7;
clk_div = DFFE(clk_div_lut_out, clk, , , );


--udreg is udreg
--operation mode is normal

udreg_lut_out = !udreg;
udreg = DFFE(udreg_lut_out, up_down, , , );


--A1L46 is hex[0]~49COMB
--operation mode is arithmetic

A1L46 = VCC;

--A1L56 is hex[0]~51
--operation mode is arithmetic

A1L56 = CARRY(!udreg);


--counter[23] is counter[23]
--operation mode is counter

counter[23]_lut_out = counter[23] $ (A1L75);
counter[23]_reg_input = !A1L7 & counter[23]_lut_out;
counter[23] = DFFE(counter[23]_reg_input, clk, , , );

--A1L95 is counter[23]~284
--operation mode is counter

A1L95 = CARRY(!A1L75 # !counter[23]);


--counter[24] is counter[24]
--operation mode is normal

counter[24]_lut_out = counter[24] $ (!A1L95);
counter[24]_reg_input = !A1L7 & counter[24]_lut_out;
counter[24] = DFFE(counter[24]_reg_input, clk, , , );


--counter[16] is counter[16]
--operation mode is counter

counter[16]_lut_out = counter[16] $ (!A1L34);
counter[16]_reg_input = !A1L7 & counter[16]_lut_out;
counter[16] = DFFE(counter[16]_reg_input, clk, , , );

--A1L54 is counter[16]~290
--operation mode is counter

A1L54 = CARRY(counter[16] & (!A1L34));


--counter[17] is counter[17]
--operation mode is counter

counter[17]_lut_out = counter[17] $ (A1L54);
counter[17]_reg_input = !A1L7 & counter[17]_lut_out;
counter[17] = DFFE(counter[17]_reg_input, clk, , , );

--A1L74 is counter[17]~293
--operation mode is counter

A1L74 = CARRY(!A1L54 # !counter[17]);


--counter[15] is counter[15]
--operation mode is counter

counter[15]_lut_out = counter[15] $ (A1L14);
counter[15]_reg_input = !A1L7 & counter[15]_lut_out;
counter[15] = DFFE(counter[15]_reg_input, clk, , , );

--A1L34 is counter[15]~296
--operation mode is counter

A1L34 = CARRY(!A1L14 # !counter[15]);


--counter[18] is counter[18]
--operation mode is counter

counter[18]_lut_out = counter[18] $ (!A1L74);
counter[18]_reg_input = !A1L7 & counter[18]_lut_out;
counter[18] = DFFE(counter[18]_reg_input, clk, , , );

--A1L94 is counter[18]~299
--operation mode is counter

A1L94 = CARRY(counter[18] & (!A1L74));


--A1L4 is LessThan~586
--operation mode is normal

A1L4 = !counter[16] & !counter[17] & !counter[15] # !counter[18];


--counter[19] is counter[19]
--operation mode is counter

counter[19]_lut_out = counter[19] $ (A1L94);
counter[19]_reg_input = !A1L7 & counter[19]_lut_out;
counter[19] = DFFE(counter[19]_reg_input, clk, , , );

--A1L15 is counter[19]~302
--operation mode is counter

A1L15 = CARRY(!A1L94 # !counter[19]);


--counter[20] is counter[20]
--operation mode is counter

counter[20]_lut_out = counter[20] $ (!A1L15);
counter[20]_reg_input = !A1L7 & counter[20]_lut_out;
counter[20] = DFFE(counter[20]_reg_input, clk, , , );

--A1L35 is counter[20]~305
--operation mode is counter

A1L35 = CARRY(counter[20] & (!A1L15));


--counter[21] is counter[21]
--operation mode is counter

counter[21]_lut_out = counter[21] $ (A1L35);
counter[21]_reg_input = !A1L7 & counter[21]_lut_out;
counter[21] = DFFE(counter[21]_reg_input, clk, , , );

--A1L55 is counter[21]~308
--operation mode is counter

A1L55 = CARRY(!A1L35 # !counter[21]);


--counter[22] is counter[22]
--operation mode is counter

counter[22]_lut_out = counter[22] $ (!A1L55);
counter[22]_reg_input = !A1L7 & counter[22]_lut_out;
counter[22] = DFFE(counter[22]_reg_input, clk, , , );

--A1L75 is counter[22]~311
--operation mode is counter

A1L75 = CARRY(counter[22] & (!A1L55));


--A1L5 is LessThan~587
--operation mode is normal

A1L5 = !counter[22] # !counter[21] # !counter[20] # !counter[19];


--A1L6 is LessThan~588
--operation mode is normal

A1L6 = counter[23] & counter[24] & !A1L4 & !A1L5;

--A1L8 is LessThan~592
--operation mode is normal

A1L8 = counter[23] & counter[24] & !A1L4 & !A1L5;


--counter[12] is counter[12]
--operation mode is counter

counter[12]_lut_out = counter[12] $ (!A1L53);
counter[12]_reg_input = !A1L7 & counter[12]_lut_out;
counter[12] = DFFE(counter[12]_reg_input, clk, , , );

--A1L73 is counter[12]~314
--operation mode is counter

A1L73 = CARRY(counter[12] & (!A1L53));


--counter[4] is counter[4]
--operation mode is counter

counter[4]_lut_out = counter[4] $ (!A1L91);
counter[4]_reg_input = !A1L7 & counter[4]_lut_out;
counter[4] = DFFE(counter[4]_reg_input, clk, , , );

--A1L12 is counter[4]~317
--operation mode is counter

A1L12 = CARRY(counter[4] & (!A1L91));


--counter[5] is counter[5]
--operation mode is counter

counter[5]_lut_out = counter[5] $ (A1L12);
counter[5]_reg_input = !A1L7 & counter[5]_lut_out;
counter[5] = DFFE(counter[5]_reg_input, clk, , , );

--A1L32 is counter[5]~320
--operation mode is counter

A1L32 = CARRY(!A1L12 # !counter[5]);


--counter[6] is counter[6]
--operation mode is counter

counter[6]_lut_out = counter[6] $ (!A1L32);
counter[6]_reg_input = !A1L7 & counter[6]_lut_out;
counter[6] = DFFE(counter[6]_reg_input, clk, , , );

--A1L52 is counter[6]~323
--operation mode is counter

A1L52 = CARRY(counter[6] & (!A1L32));


--counter[7] is counter[7]
--operation mode is counter

counter[7]_lut_out = counter[7] $ (A1L52);
counter[7]_reg_input = !A1L7 & counter[7]_lut_out;
counter[7] = DFFE(counter[7]_reg_input, clk, , , );

--A1L72 is counter[7]~326
--operation mode is counter

A1L72 = CARRY(!A1L52 # !counter[7]);


--counter[10] is counter[10]
--operation mode is counter

counter[10]_lut_out = counter[10] $ (!A1L13);
counter[10]_reg_input = !A1L7 & counter[10]_lut_out;
counter[10] = DFFE(counter[10]_reg_input, clk, , , );

--A1L33 is counter[10]~329
--operation mode is counter

A1L33 = CARRY(counter[10] & (!A1L13));


--counter[11] is counter[11]
--operation mode is counter

counter[11]_lut_out = counter[11] $ (A1L33);
counter[11]_reg_input = !A1L7 & counter[11]_lut_out;
counter[11] = DFFE(counter[11]_reg_input, clk, , , );

--A1L53 is counter[11]~332
--operation mode is counter

A1L53 = CARRY(!A1L33 # !counter[11]);


--counter[8] is counter[8]
--operation mode is counter

counter[8]_lut_out = counter[8] $ (!A1L72);
counter[8]_reg_input = !A1L7 & counter[8]_lut_out;
counter[8] = DFFE(counter[8]_reg_input, clk, , , );

--A1L92 is counter[8]~335
--operation mode is counter

A1L92 = CARRY(counter[8] & (!A1L72));


--counter[9] is counter[9]
--operation mode is counter

counter[9]_lut_out = counter[9] $ (A1L92);
counter[9]_reg_input = !A1L7 & counter[9]_lut_out;
counter[9] = DFFE(counter[9]_reg_input, clk, , , );

--A1L13 is counter[9]~338
--operation mode is counter

A1L13 = CARRY(!A1L92 # !counter[9]);


--counter[13] is counter[13]
--operation mode is counter

counter[13]_lut_out = counter[13] $ (A1L73);
counter[13]_reg_input = !A1L7 & counter[13]_lut_out;
counter[13] = DFFE(counter[13]_reg_input, clk, , , );

--A1L93 is counter[13]~341
--operation mode is counter

A1L93 = CARRY(!A1L73 # !counter[13]);


--counter[14] is counter[14]
--operation mode is counter

counter[14]_lut_out = counter[14] $ (!A1L93);
counter[14]_reg_input = !A1L7 & counter[14]_lut_out;
counter[14] = DFFE(counter[14]_reg_input, clk, , , );

--A1L14 is counter[14]~344
--operation mode is counter

A1L14 = CARRY(counter[14] & (!A1L93));


--counter[3] is counter[3]
--operation mode is counter

counter[3]_lut_out = counter[3] $ (A1L71);
counter[3]_reg_input = !A1L7 & counter[3]_lut_out;
counter[3] = DFFE(counter[3]_reg_input, clk, , , );

--A1L91 is counter[3]~347
--operation mode is counter

A1L91 = CARRY(!A1L71 # !counter[3]);


--counter[2] is counter[2]
--operation mode is counter

counter[2]_lut_out = counter[2] $ (!A1L51);
counter[2]_reg_input = !A1L7 & counter[2]_lut_out;
counter[2] = DFFE(counter[2]_reg_input, clk, , , );

--A1L71 is counter[2]~350
--operation mode is counter

A1L71 = CARRY(counter[2] & (!A1L51));


--counter[1] is counter[1]
--operation mode is counter

counter[1]_lut_out = counter[1] $ (A1L31);
counter[1]_reg_input = !A1L7 & counter[1]_lut_out;
counter[1] = DFFE(counter[1]_reg_input, clk, , , );

--A1L51 is counter[1]~353
--operation mode is counter

A1L51 = CARRY(!A1L31 # !counter[1]);


--counter[0] is counter[0]
--operation mode is counter

counter[0]_lut_out = !counter[0];
counter[0]_reg_input = !A1L7 & counter[0]_lut_out;
counter[0] = DFFE(counter[0]_reg_input, clk, , , );

--A1L31 is counter[0]~356
--operation mode is counter

A1L31 = CARRY(counter[0]);


--A1L7 is LessThan~590
--operation mode is normal

A1L7 = (A1L1 # counter[13] # counter[17] # counter[16]) & CASCADE(A1L8);


--A1L1 is LessThan~556
--operation mode is normal

A1L1 = counter[14] # counter[12] & (A1L2 # counter[10]);


--A1L2 is LessThan~559
--operation mode is normal

A1L2 = counter[11] # A1L3 & counter[9] & counter[8];


--A1L3 is LessThan~562
--operation mode is normal

A1L3 = counter[7] # counter[6] & (counter[5] # counter[4]);


--clk is clk
--operation mode is input

clk = INPUT();


--up_down is up_down
--operation mode is input

up_down = INPUT();


--seg[0] is seg[0]
--operation mode is output

seg[0] = OUTPUT(A1L37Q);


--seg[1] is seg[1]
--operation mode is output

seg[1] = OUTPUT(A1L57Q);


--seg[2] is seg[2]
--operation mode is output

seg[2] = OUTPUT(A1L77Q);


--seg[3] is seg[3]
--operation mode is output

seg[3] = OUTPUT(A1L97Q);


--seg[4] is seg[4]
--operation mode is output

seg[4] = OUTPUT(A1L18Q);


--seg[5] is seg[5]
--operation mode is output

seg[5] = OUTPUT(A1L38Q);


--seg[6] is seg[6]
--operation mode is output

seg[6] = OUTPUT(A1L58Q);


--seg[7] is seg[7]
--operation mode is output

seg[7] = OUTPUT(VCC);