?? invmod_test.v
字號:
module InvMod_test(
data,
q,
wraddr,
rdaddr,
wren,
rden,
clk,
Rst_n,
start,
done
);
input clk,Rst_n;
input [31:0] data;
input start;
input rden,wren;
output [31:0] q;
output done;
input [9:0] wraddr,rdaddr;
wire InvMod_rden,InvMod_wren;
wire [31:0] InvMod_data,InvMod_q;
wire [9:0] InvMod_rdaddr,InvMod_wraddr;
wire InvMod_valid;
wire [9:0] InvMod_a_addr,InvMod_D_addr;
assign InvMod_a_addr = 10'b00_1000_0000;
assign InvMod_D_addr = 10'b01_1000_0000;
InvMod M1(
.clk(clk),
.Rst_n(Rst_n),
.InvMod_wren(InvMod_wren),
.InvMod_rden(InvMod_rden),
.InvMod_wraddr(InvMod_wraddr),
.InvMod_rdaddr(InvMod_rdaddr),
.InvMod_q(InvMod_q),
.InvMod_data(InvMod_data),
.InvMod_valid(InvMod_valid),
.InvMod_start(start),
.InvMod_done(done),
.InvMod_a_addr(InvMod_a_addr),
.InvMod_D_addr(InvMod_D_addr)
);
wire [31:0] temp_data,q_ram;
wire [31:0] temp_rdaddr,temp_wraddr;
wire [9:0] temp_wren,temp_rden;
//assign q = q_ram;
assign temp_data =(InvMod_valid==1'b1)? InvMod_data:data;
assign temp_rden =(InvMod_valid==1'b1)? InvMod_rden:rden;
assign temp_wren =(InvMod_valid==1'b1)? InvMod_wren:wren;
assign temp_rdaddr = (InvMod_valid==1'b1)? InvMod_rdaddr:rdaddr;
assign temp_wraddr = (InvMod_valid==1'b1)? InvMod_wraddr:wraddr;
assign q = q_ram;
assign InvMod_q = q_ram;
RAM_InvMod myram
(
.data(temp_data),
.wren(temp_wren),
.wraddress(temp_wraddr),
.rdaddress(temp_rdaddr),
.rden(temp_rden),
.clock(clk),
.q(q_ram)
);
endmodule
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