library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity rx8 is port(
		rst				: in std_logic;
		p1mhz			: in std_logic;
		rx				: in std_logic;
		data_out		: out std_logic_vector(7 downto 0);
		rx_tag			: out std_logic;
		SA				: in std_logic_vector(15 downto 0);
		ior				: in std_logic
);
end entity	;

architecture rx of rx8 is
		
component data_clk is port (
		rst				: in std_logic;
		p1mhz			: in std_logic;
		can_data_clk	: in std_logic;
		data_clk		: out std_logic		
);
end component;

signal data_cnt : integer range 0 to 11;
constant data_cnt_limit : integer := 12; 

signal rx_clk : std_logic;
signal beg_rx,end_rx : std_logic;
signal en_rx,en_rx_end : std_logic;
-----------------------------------
signal t_data : std_logic_vector(11 downto 0);
signal t_rx_tag : std_logic;

begin	


u_data_clk : data_clk port map(
		rst				=> rst,--: in std_logic;
		p1mhz			=> p1mhz,--: in std_logic;
		can_data_clk	=> en_rx,--: in std_logic;
		data_clk		=> rx_clk);--: out std_logic--;
	

stup_en_rx :process(rst,rx,en_rx_end)
begin
	if rst='0' or en_rx_end='1' then
		en_rx <= '0';
	else
		if falling_edge(rx) then
			if data_cnt=0 then
			 	en_rx <= '1';
			end if;
		end if;
	end if;		
end process;

gen_write_data_cnt : process(rst,en_rx,rx_clk) 
begin
	if rst='0' or en_rx='0' then
		en_rx_end <= '0';
		data_cnt <= 0;
	else
		if rising_edge(rx_clk) then	
			if en_rx = '1' and data_cnt < data_cnt_limit then
				data_cnt <= data_cnt + 1;
			else
				en_rx_end <= '1';	
			end if;
		end if;
	end if;			
end process;

write_data : process(rst,rx_clk,rx)
begin
	if rst='0' then
		t_data <= (others=>'0');
	else
		if falling_edge(rx_clk) then
			if en_rx = '1' then
				case data_cnt is
					when 0 =>
						t_data <= "00000000000" & rx;
					when 1 =>
						t_data <= "0000000000" & rx & t_data(0);
					when 2 =>
						t_data <= "000000000" & rx & t_data(1 downto 0);		
					when 3 =>
						t_data <= "00000000" & rx & t_data(2 downto 0);	
					when 4 =>
						t_data <= "0000000" & rx & t_data(3 downto 0);	
					when 5 =>
						t_data <= "000000" & rx & t_data(4 downto 0);	
					when 6 =>
						t_data <= "00000" & rx & t_data(5 downto 0);	
					when 7 =>
						t_data <= "0000" & rx & t_data(6 downto 0);	
					when 8 =>
						t_data <= "000" & rx & t_data(7 downto 0);	
					when 9 =>
						t_data <= "00" & rx & t_data(8 downto 0);	
					when 10 =>
						t_data <= "0" & rx & t_data(9 downto 0);	
					when 11 =>
						t_data <= rx & t_data(10 downto 0);	
					when others =>
						t_data <= t_data;							
				end case;	
			end if;
		end if;
	end if;		
end process;


process(rst,sa,ior,en_rx)
begin
	if rst='0' or (sa=x"c021" and ior='0') then
		t_rx_tag <= '0';	
	else
		if falling_edge(en_rx) then	
			if t_data(0)='0' and t_data(10)='1' then
				t_rx_tag <= '1';
			end if;	
		end if;
	end if;		
end process;

rx_tag <= t_rx_tag;
data_out <= t_data(8 downto 1)  ;


end architecture ;