iow => data_out[3]~reg0.CLK
iow => data_out[2]~reg0.CLK
iow => data_out[1]~reg0.CLK
iow => data_out[0]~reg0.CLK
iow => data_out[7]~reg0.CLK
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
cs => data_out[6]~reg0.ENA
cs => data_out[5]~reg0.ENA
cs => data_out[4]~reg0.ENA
cs => data_out[3]~reg0.ENA
cs => data_out[2]~reg0.ENA
cs => data_out[1]~reg0.ENA
cs => data_out[0]~reg0.ENA
cs => data_out[7]~reg0.ENA
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|do_adc:u_ad
rst => sig_adc:u_sig_adc.rst
rst => wri_reg8:u_sel_read_ch.rst
rst => st[3].ACLR
rst => st[2].ACLR
rst => st[1].ACLR
rst => st[0].ACLR
rst => ad_data_lchk[11].ACLR
rst => ad_data_lchk[10].ACLR
rst => ad_data_lchk[9].ACLR
rst => ad_data_lchk[8].ACLR
rst => ad_data_lchk[7].ACLR
rst => ad_data_lchk[6].ACLR
rst => ad_data_lchk[5].ACLR
rst => ad_data_lchk[4].ACLR
rst => ad_data_lchk[3].ACLR
rst => ad_data_lchk[2].ACLR
rst => ad_data_lchk[1].ACLR
rst => ad_data_lchk[0].ACLR
rst => ad_data_sd[11].ACLR
rst => ad_data_sd[10].ACLR
rst => ad_data_sd[9].ACLR
rst => ad_data_sd[8].ACLR
rst => ad_data_sd[7].ACLR
rst => ad_data_sd[6].ACLR
rst => ad_data_sd[5].ACLR
rst => ad_data_sd[4].ACLR
rst => ad_data_sd[3].ACLR
rst => ad_data_sd[2].ACLR
rst => ad_data_sd[1].ACLR
rst => ad_data_sd[0].ACLR
rst => ad_data_cm[11].ACLR
rst => ad_data_cm[10].ACLR
rst => ad_data_cm[9].ACLR
rst => ad_data_cm[8].ACLR
rst => ad_data_cm[7].ACLR
rst => ad_data_cm[6].ACLR
rst => ad_data_cm[5].ACLR
rst => ad_data_cm[4].ACLR
rst => ad_data_cm[3].ACLR
rst => ad_data_cm[2].ACLR
rst => ad_data_cm[1].ACLR
rst => ad_data_cm[0].ACLR
rst => ad_data_P28[11].ACLR
rst => ad_data_P28[10].ACLR
rst => ad_data_P28[9].ACLR
rst => ad_data_P28[8].ACLR
rst => ad_data_P28[7].ACLR
rst => ad_data_P28[6].ACLR
rst => ad_data_P28[5].ACLR
rst => ad_data_P28[4].ACLR
rst => ad_data_P28[3].ACLR
rst => ad_data_P28[2].ACLR
rst => ad_data_P28[1].ACLR
rst => ad_data_P28[0].ACLR
rst => ad_data_N28[11].ACLR
rst => ad_data_N28[10].ACLR
rst => ad_data_N28[9].ACLR
rst => ad_data_N28[8].ACLR
rst => ad_data_N28[7].ACLR
rst => ad_data_N28[6].ACLR
rst => ad_data_N28[5].ACLR
rst => ad_data_N28[4].ACLR
rst => ad_data_N28[3].ACLR
rst => ad_data_N28[2].ACLR
rst => ad_data_N28[1].ACLR
rst => ad_data_N28[0].ACLR
rst => ad_data_V5[11].ACLR
rst => ad_data_V5[10].ACLR
rst => ad_data_V5[9].ACLR
rst => ad_data_V5[8].ACLR
rst => ad_data_V5[7].ACLR
rst => ad_data_V5[6].ACLR
rst => ad_data_V5[5].ACLR
rst => ad_data_V5[4].ACLR
rst => ad_data_V5[3].ACLR
rst => ad_data_V5[2].ACLR
rst => ad_data_V5[1].ACLR
rst => ad_data_V5[0].ACLR
rst => adc_state[7]~reg0.ACLR
rst => st[4].ACLR
rst => t_cda[6].ACLR
rst => t_cda[5].ACLR
rst => t_cda[4].ACLR
rst => t_cda[3].ACLR
rst => t_cda[2].ACLR
rst => t_cda[1].ACLR
rst => t_cda[0].ACLR
rst => t_sig_adc.PRESET
rst => t_can_con_adc_end.ACLR
rst => adc_state[6]~reg0.ACLR
rst => adc_state[5]~reg0.ACLR
rst => adc_state[4]~reg0.ACLR
rst => adc_state[3]~reg0.ACLR
rst => adc_state[2]~reg0.ACLR
rst => adc_state[1]~reg0.ACLR
rst => adc_state[0]~reg0.ACLR
rst => setup_adc_tag~0.IN0
rst => t_cda[7].ACLR
sa[0] => reduce_nor~0.IN13
sa[0] => sig_adc:u_sig_adc.sa[0]
sa[0] => reduce_nor~7.IN13
sa[1] => reduce_nor~0.IN12
sa[1] => reduce_nor~7.IN12
sa[1] => sig_adc:u_sig_adc.sa[1]
sa[2] => reduce_nor~0.IN11
sa[2] => reduce_nor~7.IN11
sa[2] => sig_adc:u_sig_adc.sa[2]
sa[3] => reduce_nor~0.IN10
sa[3] => reduce_nor~7.IN10
sa[3] => sig_adc:u_sig_adc.sa[3]
sa[4] => reduce_nor~0.IN9
sa[4] => reduce_nor~7.IN9
sa[4] => sig_adc:u_sig_adc.sa[4]
sa[5] => reduce_nor~0.IN8
sa[5] => reduce_nor~7.IN8
sa[5] => sig_adc:u_sig_adc.sa[5]
sa[6] => reduce_nor~0.IN7
sa[6] => reduce_nor~7.IN7
sa[6] => sig_adc:u_sig_adc.sa[6]
sa[7] => reduce_nor~0.IN6
sa[7] => reduce_nor~7.IN6
sa[7] => sig_adc:u_sig_adc.sa[7]
sa[8] => reduce_nor~0.IN5
sa[8] => reduce_nor~7.IN5
sa[8] => sig_adc:u_sig_adc.sa[8]
sa[9] => reduce_nor~0.IN4
sa[9] => reduce_nor~7.IN4
sa[9] => sig_adc:u_sig_adc.sa[9]
sa[10] => reduce_nor~0.IN3
sa[10] => reduce_nor~7.IN3
sa[10] => sig_adc:u_sig_adc.sa[10]
sa[11] => reduce_nor~0.IN2
sa[11] => reduce_nor~7.IN2
sa[11] => sig_adc:u_sig_adc.sa[11]
sa[12] => reduce_nor~0.IN1
sa[12] => reduce_nor~7.IN1
sa[12] => sig_adc:u_sig_adc.sa[12]
sa[13] => reduce_nor~0.IN0
sa[13] => reduce_nor~7.IN0
sa[13] => sig_adc:u_sig_adc.sa[13]
sa[14] => sig_adc:u_sig_adc.sa[14]
sa[14] => reduce_nor~0.IN14
sa[14] => reduce_nor~7.IN14
sa[15] => sig_adc:u_sig_adc.sa[15]
sa[15] => reduce_nor~0.IN15
sa[15] => reduce_nor~7.IN15
ad_in[0] => sig_adc:u_sig_adc.ad_in[0]
ad_in[0] => wri_reg8:u_sel_read_ch.data_in[0]
ad_in[0] => reduce_nor~8.IN7
ad_in[1] => sig_adc:u_sig_adc.ad_in[1]
ad_in[1] => wri_reg8:u_sel_read_ch.data_in[1]
ad_in[1] => reduce_nor~8.IN6
ad_in[2] => sig_adc:u_sig_adc.ad_in[2]
ad_in[2] => wri_reg8:u_sel_read_ch.data_in[2]
ad_in[2] => reduce_nor~8.IN5
ad_in[3] => reduce_nor~8.IN4
ad_in[3] => sig_adc:u_sig_adc.ad_in[3]
ad_in[3] => wri_reg8:u_sel_read_ch.data_in[3]
ad_in[4] => reduce_nor~8.IN3
ad_in[4] => sig_adc:u_sig_adc.ad_in[4]
ad_in[4] => wri_reg8:u_sel_read_ch.data_in[4]
ad_in[5] => reduce_nor~8.IN2
ad_in[5] => sig_adc:u_sig_adc.ad_in[5]
ad_in[5] => wri_reg8:u_sel_read_ch.data_in[5]
ad_in[6] => reduce_nor~8.IN1
ad_in[6] => sig_adc:u_sig_adc.ad_in[6]
ad_in[6] => wri_reg8:u_sel_read_ch.data_in[6]
ad_in[7] => reduce_nor~8.IN0
ad_in[7] => sig_adc:u_sig_adc.ad_in[7]
ad_in[7] => wri_reg8:u_sel_read_ch.data_in[7]
iow => sig_adc:u_sig_adc.iow
iow => wri_reg8:u_sel_read_ch.iow
iow => t_can_con_adc.CLK
p12mhz => t_cda[6].CLK
p12mhz => t_cda[5].CLK
p12mhz => t_cda[4].CLK
p12mhz => t_cda[3].CLK
p12mhz => t_cda[2].CLK
p12mhz => t_cda[1].CLK
p12mhz => t_cda[0].CLK
p12mhz => t_sig_adc.CLK
p12mhz => t_can_con_adc_end.CLK
p12mhz => st[4].CLK
p12mhz => st[3].CLK
p12mhz => st[2].CLK
p12mhz => st[1].CLK
p12mhz => st[0].CLK
p12mhz => ad_data_lchk[11].CLK
p12mhz => ad_data_lchk[10].CLK
p12mhz => ad_data_lchk[9].CLK
p12mhz => ad_data_lchk[8].CLK
p12mhz => ad_data_lchk[7].CLK
p12mhz => ad_data_lchk[6].CLK
p12mhz => ad_data_lchk[5].CLK
p12mhz => ad_data_lchk[4].CLK
p12mhz => ad_data_lchk[3].CLK
p12mhz => ad_data_lchk[2].CLK
p12mhz => ad_data_lchk[1].CLK
p12mhz => ad_data_lchk[0].CLK
p12mhz => ad_data_sd[11].CLK
p12mhz => ad_data_sd[10].CLK
p12mhz => ad_data_sd[9].CLK
p12mhz => ad_data_sd[8].CLK
p12mhz => ad_data_sd[7].CLK
p12mhz => ad_data_sd[6].CLK
p12mhz => ad_data_sd[5].CLK
p12mhz => ad_data_sd[4].CLK
p12mhz => ad_data_sd[3].CLK
p12mhz => ad_data_sd[2].CLK
p12mhz => ad_data_sd[1].CLK
p12mhz => ad_data_sd[0].CLK
p12mhz => ad_data_cm[11].CLK
p12mhz => ad_data_cm[10].CLK
p12mhz => ad_data_cm[9].CLK
p12mhz => ad_data_cm[8].CLK
p12mhz => ad_data_cm[7].CLK
p12mhz => ad_data_cm[6].CLK
p12mhz => ad_data_cm[5].CLK
p12mhz => ad_data_cm[4].CLK
p12mhz => ad_data_cm[3].CLK
p12mhz => ad_data_cm[2].CLK
p12mhz => ad_data_cm[1].CLK
p12mhz => ad_data_cm[0].CLK
p12mhz => ad_data_P28[11].CLK
p12mhz => ad_data_P28[10].CLK
p12mhz => ad_data_P28[9].CLK
p12mhz => ad_data_P28[8].CLK
p12mhz => ad_data_P28[7].CLK
p12mhz => ad_data_P28[6].CLK
p12mhz => ad_data_P28[5].CLK
p12mhz => ad_data_P28[4].CLK
p12mhz => ad_data_P28[3].CLK
p12mhz => ad_data_P28[2].CLK
p12mhz => ad_data_P28[1].CLK
p12mhz => ad_data_P28[0].CLK
p12mhz => ad_data_N28[11].CLK
p12mhz => ad_data_N28[10].CLK
p12mhz => ad_data_N28[9].CLK
p12mhz => ad_data_N28[8].CLK
p12mhz => ad_data_N28[7].CLK
p12mhz => ad_data_N28[6].CLK
p12mhz => ad_data_N28[5].CLK
p12mhz => ad_data_N28[4].CLK
p12mhz => ad_data_N28[3].CLK
p12mhz => ad_data_N28[2].CLK
p12mhz => ad_data_N28[1].CLK
p12mhz => ad_data_N28[0].CLK
p12mhz => ad_data_V5[11].CLK
p12mhz => ad_data_V5[10].CLK
p12mhz => ad_data_V5[9].CLK
p12mhz => ad_data_V5[8].CLK
p12mhz => ad_data_V5[7].CLK
p12mhz => ad_data_V5[6].CLK
p12mhz => ad_data_V5[5].CLK
p12mhz => ad_data_V5[4].CLK
p12mhz => ad_data_V5[3].CLK
p12mhz => ad_data_V5[2].CLK
p12mhz => ad_data_V5[1].CLK
p12mhz => ad_data_V5[0].CLK
p12mhz => adc_state[7]~reg0.CLK
p12mhz => adc_state[6]~reg0.CLK
p12mhz => adc_state[5]~reg0.CLK
p12mhz => adc_state[4]~reg0.CLK
p12mhz => adc_state[3]~reg0.CLK
p12mhz => adc_state[2]~reg0.CLK
p12mhz => adc_state[1]~reg0.CLK
p12mhz => adc_state[0]~reg0.CLK
p12mhz => sig_adc:u_sig_adc.p12mhz
p12mhz => t_cda[7].CLK
cda[0] <= cda~2.DB_MAX_OUTPUT_PORT_TYPE
cda[1] <= cda~1.DB_MAX_OUTPUT_PORT_TYPE
cda[2] <= cda~0.DB_MAX_OUTPUT_PORT_TYPE
eoc_state => sig_adc:u_sig_adc.eoc_state
sd[0] => sig_adc:u_sig_adc.sd[0]
sd[1] => sig_adc:u_sig_adc.sd[1]
sd[2] => sig_adc:u_sig_adc.sd[2]
sd[3] => sig_adc:u_sig_adc.sd[3]
sd[4] => sig_adc:u_sig_adc.sd[4]
sd[5] => sig_adc:u_sig_adc.sd[5]
sd[6] => sig_adc:u_sig_adc.sd[6]
sd[7] => sig_adc:u_sig_adc.sd[7]
rd_adl <= sig_adc:u_sig_adc.rd_adl
rd_adh <= sig_adc:u_sig_adc.rd_adh
start_ad <= sig_adc:u_sig_adc.start_ad
adc_state[0] <= adc_state[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[1] <= adc_state[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[2] <= adc_state[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[3] <= adc_state[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[4] <= adc_state[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[5] <= adc_state[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[6] <= adc_state[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[7] <= adc_state[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
lchk_level[0] <= t_lchk_level~2.DB_MAX_OUTPUT_PORT_TYPE
lchk_level[1] <= t_lchk_level~1.DB_MAX_OUTPUT_PORT_TYPE
p28v_level <= t_p28v_level~0.DB_MAX_OUTPUT_PORT_TYPE
n28v_level <= t_n28v_level~0.DB_MAX_OUTPUT_PORT_TYPE
ref5v_level <= t_ref5v_level~0.DB_MAX_OUTPUT_PORT_TYPE
cm_level[0] <= t_cm_level~41.DB_MAX_OUTPUT_PORT_TYPE
cm_level[1] <= t_cm_level~40.DB_MAX_OUTPUT_PORT_TYPE
cm_level[2] <= t_cm_level~39.DB_MAX_OUTPUT_PORT_TYPE
cm_level[3] <= t_cm_level~38.DB_MAX_OUTPUT_PORT_TYPE
sd_level[0] <= t_sd_level~16.DB_MAX_OUTPUT_PORT_TYPE
sd_level[1] <= t_sd_level~15.DB_MAX_OUTPUT_PORT_TYPE
sd_level[2] <= t_sd_level~14.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[0] <= x_ad_data~71.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[1] <= x_ad_data~70.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[2] <= x_ad_data~69.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[3] <= x_ad_data~68.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[4] <= x_ad_data~67.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[5] <= x_ad_data~66.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[6] <= x_ad_data~65.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[7] <= x_ad_data~64.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[8] <= x_ad_data~63.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[9] <= x_ad_data~62.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[10] <= x_ad_data~61.DB_MAX_OUTPUT_PORT_TYPE
x_ad_data[11] <= x_ad_data~60.DB_MAX_OUTPUT_PORT_TYPE


|cpu|do_adc:u_ad|wri_reg8:u_sel_read_ch
iow => data_out[6]~reg0.CLK
iow => data_out[5]~reg0.CLK
iow => data_out[4]~reg0.CLK
iow => data_out[3]~reg0.CLK
iow => data_out[2]~reg0.CLK
iow => data_out[1]~reg0.CLK
iow => data_out[0]~reg0.CLK
iow => data_out[7]~reg0.CLK
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
cs => data_out[6]~reg0.ENA
cs => data_out[5]~reg0.ENA
cs => data_out[4]~reg0.ENA
cs => data_out[3]~reg0.ENA
cs => data_out[2]~reg0.ENA
cs => data_out[1]~reg0.ENA
cs => data_out[0]~reg0.ENA
cs => data_out[7]~reg0.ENA
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|do_adc:u_ad|sig_adc:u_sig_adc
rst => st[3].ACLR
rst => st[2].ACLR
rst => st[1].ACLR
rst => st[0].ACLR
rst => gen_t_sig_adc_end_tag~0.IN0
rst => rd_adh~reg0.PRESET
rst => ad_charge_time[10].ACLR
rst => ad_charge_time[9].ACLR
rst => ad_charge_time[8].ACLR
rst => ad_charge_time[7].ACLR