rst => ad_charge_time[6].ACLR
rst => ad_charge_time[5].ACLR
rst => ad_charge_time[4].ACLR
rst => ad_charge_time[3].ACLR
rst => ad_charge_time[2].ACLR
rst => ad_charge_time[1].ACLR
rst => ad_charge_time[0].ACLR
rst => ad_delay_time[9].ACLR
rst => ad_delay_time[8].ACLR
rst => ad_delay_time[7].ACLR
rst => ad_delay_time[6].ACLR
rst => ad_delay_time[5].ACLR
rst => ad_delay_time[4].ACLR
rst => ad_delay_time[3].ACLR
rst => ad_delay_time[2].ACLR
rst => ad_delay_time[1].ACLR
rst => ad_delay_time[0].ACLR
rst => t_sig_adc_end.ACLR
rst => adc_state[6]~reg0.ACLR
rst => adc_state[5]~reg0.ACLR
rst => adc_state[4]~reg0.ACLR
rst => adc_state[3]~reg0.ACLR
rst => adc_state[2]~reg0.ACLR
rst => adc_state[1]~reg0.ACLR
rst => adc_state[0]~reg0.ACLR
rst => st[4].ACLR
rst => adc_state[7]~reg0.ACLR
rst => rd_adl~reg0.PRESET
rst => start_ad~reg0.ENA
rst => ad_data[11]~reg0.ENA
rst => ad_data[10]~reg0.ENA
rst => ad_data[9]~reg0.ENA
rst => ad_data[8]~reg0.ENA
rst => ad_data[7]~reg0.ENA
rst => ad_data[6]~reg0.ENA
rst => ad_data[5]~reg0.ENA
rst => ad_data[4]~reg0.ENA
rst => ad_data[3]~reg0.ENA
rst => ad_data[2]~reg0.ENA
rst => ad_data[1]~reg0.ENA
rst => ad_data[0]~reg0.ENA
sa[0] => ~NO_FANOUT~
sa[1] => ~NO_FANOUT~
sa[2] => ~NO_FANOUT~
sa[3] => ~NO_FANOUT~
sa[4] => ~NO_FANOUT~
sa[5] => ~NO_FANOUT~
sa[6] => ~NO_FANOUT~
sa[7] => ~NO_FANOUT~
sa[8] => ~NO_FANOUT~
sa[9] => ~NO_FANOUT~
sa[10] => ~NO_FANOUT~
sa[11] => ~NO_FANOUT~
sa[12] => ~NO_FANOUT~
sa[13] => ~NO_FANOUT~
sa[14] => ~NO_FANOUT~
sa[15] => ~NO_FANOUT~
ad_in[0] => ~NO_FANOUT~
ad_in[1] => ~NO_FANOUT~
ad_in[2] => ~NO_FANOUT~
ad_in[3] => ~NO_FANOUT~
ad_in[4] => ~NO_FANOUT~
ad_in[5] => ~NO_FANOUT~
ad_in[6] => ~NO_FANOUT~
ad_in[7] => ~NO_FANOUT~
can_adc => t_sig_adc.CLK
iow => ~NO_FANOUT~
p12mhz => rd_adh~reg0.CLK
p12mhz => ad_charge_time[10].CLK
p12mhz => ad_charge_time[9].CLK
p12mhz => ad_charge_time[8].CLK
p12mhz => ad_charge_time[7].CLK
p12mhz => ad_charge_time[6].CLK
p12mhz => ad_charge_time[5].CLK
p12mhz => ad_charge_time[4].CLK
p12mhz => ad_charge_time[3].CLK
p12mhz => ad_charge_time[2].CLK
p12mhz => ad_charge_time[1].CLK
p12mhz => ad_charge_time[0].CLK
p12mhz => ad_delay_time[9].CLK
p12mhz => ad_delay_time[8].CLK
p12mhz => ad_delay_time[7].CLK
p12mhz => ad_delay_time[6].CLK
p12mhz => ad_delay_time[5].CLK
p12mhz => ad_delay_time[4].CLK
p12mhz => ad_delay_time[3].CLK
p12mhz => ad_delay_time[2].CLK
p12mhz => ad_delay_time[1].CLK
p12mhz => ad_delay_time[0].CLK
p12mhz => t_sig_adc_end.CLK
p12mhz => adc_state[7]~reg0.CLK
p12mhz => adc_state[6]~reg0.CLK
p12mhz => adc_state[5]~reg0.CLK
p12mhz => adc_state[4]~reg0.CLK
p12mhz => adc_state[3]~reg0.CLK
p12mhz => adc_state[2]~reg0.CLK
p12mhz => adc_state[1]~reg0.CLK
p12mhz => adc_state[0]~reg0.CLK
p12mhz => st[4].CLK
p12mhz => st[3].CLK
p12mhz => st[2].CLK
p12mhz => st[1].CLK
p12mhz => st[0].CLK
p12mhz => start_ad~reg0.CLK
p12mhz => ad_data[11]~reg0.CLK
p12mhz => ad_data[10]~reg0.CLK
p12mhz => ad_data[9]~reg0.CLK
p12mhz => ad_data[8]~reg0.CLK
p12mhz => ad_data[7]~reg0.CLK
p12mhz => ad_data[6]~reg0.CLK
p12mhz => ad_data[5]~reg0.CLK
p12mhz => ad_data[4]~reg0.CLK
p12mhz => ad_data[3]~reg0.CLK
p12mhz => ad_data[2]~reg0.CLK
p12mhz => ad_data[1]~reg0.CLK
p12mhz => ad_data[0]~reg0.CLK
p12mhz => rd_adl~reg0.CLK
eoc_state => t_t_sig_adc_end_tag.CLK
sd[0] => Mux~41.IN0
sd[0] => Mux~49.IN0
sd[1] => Mux~40.IN0
sd[1] => Mux~48.IN0
sd[2] => Mux~39.IN0
sd[2] => Mux~47.IN0
sd[3] => Mux~38.IN0
sd[3] => Mux~46.IN0
sd[4] => Mux~45.IN0
sd[5] => Mux~44.IN0
sd[6] => Mux~43.IN0
sd[7] => Mux~42.IN0
rd_adl <= rd_adl~reg0.DB_MAX_OUTPUT_PORT_TYPE
rd_adh <= rd_adh~reg0.DB_MAX_OUTPUT_PORT_TYPE
start_ad <= start_ad~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[0] <= adc_state[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[1] <= adc_state[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[2] <= adc_state[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[3] <= adc_state[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[4] <= adc_state[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[5] <= adc_state[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[6] <= adc_state[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
adc_state[7] <= adc_state[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[0] <= ad_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[1] <= ad_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[2] <= ad_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[3] <= ad_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[4] <= ad_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[5] <= ad_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[6] <= ad_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[7] <= ad_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[8] <= ad_data[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[9] <= ad_data[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[10] <= ad_data[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ad_data[11] <= ad_data[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|read_return_pre_set:u_rx_tx
rst => tx16:u_tx.rst
rst => rx16:u_rx.rst
rst => process0~0.IN0
rst => setup_rst_rx~0.IN0
cm_code[0] <= rx16:u_rx.data_out[12]
cm_code[1] <= rx16:u_rx.data_out[13]
cm_code[2] <= rx16:u_rx.data_out[14]
cm_code[3] <= rx16:u_rx.data_out[15]
mode <= rx16:u_rx.data_out[8]
set_key <= rx16:u_rx.data_out[7]
sd_code[0] <= rx16:u_rx.data_out[0]
sd_code[1] <= rx16:u_rx.data_out[1]
sd_code[2] <= rx16:u_rx.data_out[2]
sd_code[3] <= rx16:u_rx.data_out[3]
cm_err_code[0] => t_tx_temp[12].DATAB
cm_err_code[1] => t_tx_temp[13].DATAB
cm_err_code[2] => t_tx_temp[14].DATAB
cm_err_code[3] => t_tx_temp[15].DATAB
sd_err_code[0] => t_tx_temp[0].DATAB
sd_err_code[1] => t_tx_temp[1].DATAB
sd_err_code[2] => t_tx_temp[2].DATAB
sd_err_code[3] => t_tx_temp[3].DATAB
TC => tx16:u_tx.data_in[11]
TC => t_tx_temp~0.IN1
TC => t_tx_temp~1.IN1
y7b_err_led => tx16:u_tx.data_in[6]
y7b_put_led => tx16:u_tx.data_in[4]
y7b_ready_led => tx16:u_tx.data_in[5]
p1mhz => rx_cnt[4].CLK
p1mhz => rx_cnt[3].CLK
p1mhz => rx_cnt[2].CLK
p1mhz => rx_cnt[1].CLK
p1mhz => rx_cnt[0].CLK
p1mhz => t_rst_rx.CLK
p1mhz => t_start_tx.CLK
p1mhz => t_end_rst_rx.CLK
p1mhz => tx16:u_tx.p1mhz
p1mhz => rx16:u_rx.p1mhz
p1mhz => rx_cnt[5].CLK
set_rx => rx16:u_rx.rx
set_tx <= tx16:u_tx.tx
flash_mode_led => tx16:u_tx.data_in[9]
rst_flash_mode_led <= rx16:u_rx.data_out[9]
flash_ready_led => tx16:u_tx.data_in[10]
XT => t_tx_temp~0.IN0
XT => t_tx_temp[8].OUTPUTSELECT
XT => t_tx_temp~1.IN0
XT_MODE => t_tx_temp[8].DATAB


|cpu|read_return_pre_set:u_rx_tx|rx16:u_rx
rst => data_clk:u_data_clk.rst
rst => t_data[16].ACLR
rst => t_data[15].ACLR
rst => t_data[14].ACLR
rst => t_data[13].ACLR
rst => t_data[12].ACLR
rst => t_data[11].ACLR
rst => t_data[10].ACLR
rst => t_data[9].ACLR
rst => t_data[8].ACLR
rst => t_data[7].ACLR
rst => t_data[6].ACLR
rst => t_data[5].ACLR
rst => t_data[4].ACLR
rst => t_data[3].ACLR
rst => t_data[2].ACLR
rst => t_data[1].ACLR
rst => t_data[0].ACLR
rst => process0~0.IN0
rst => t_data[17].ACLR
rst => gen_write_data_cnt~0.IN0
rst => stup_en_rx~0.IN0
p1mhz => data_clk:u_data_clk.p1mhz
rx => en_rx.CLK
rx => t_data[17].DATAIN
rx => t_data[16].DATAIN
rx => t_data[15].DATAIN
rx => t_data[14].DATAIN
rx => t_data[13].DATAIN
rx => t_data[12].DATAIN
rx => t_data[11].DATAIN
rx => t_data[10].DATAIN
rx => t_data[9].DATAIN
rx => t_data[8].DATAIN
rx => t_data[7].DATAIN
rx => t_data[6].DATAIN
rx => t_data[5].DATAIN
rx => t_data[4].DATAIN
rx => t_data[3].DATAIN
rx => t_data[2].DATAIN
rx => t_data[1].DATAIN
rx => t_data[0].DATAIN
data_out[0] <= t_data[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= t_data[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= t_data[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= t_data[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= t_data[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= t_data[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= t_data[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= t_data[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= t_data[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= t_data[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= t_data[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= t_data[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= t_data[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= t_data[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= t_data[15].DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= t_data[16].DB_MAX_OUTPUT_PORT_TYPE
rx_tag <= t_rx_tag.DB_MAX_OUTPUT_PORT_TYPE
rst_rx => process0~0.IN1


|cpu|read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk
rst => gen_clk~0.IN1
p1mhz => clk_cnt[8].CLK
p1mhz => clk_cnt[7].CLK
p1mhz => clk_cnt[6].CLK
p1mhz => clk_cnt[5].CLK
p1mhz => clk_cnt[4].CLK
p1mhz => clk_cnt[3].CLK
p1mhz => clk_cnt[2].CLK
p1mhz => clk_cnt[1].CLK
p1mhz => clk_cnt[0].CLK
p1mhz => t_clk.CLK
p1mhz => clk_cnt[9].CLK
can_data_clk => gen_clk~0.IN0
can_data_clk => clk_cnt[8].ENA
can_data_clk => clk_cnt[7].ENA
can_data_clk => clk_cnt[6].ENA
can_data_clk => clk_cnt[5].ENA
can_data_clk => clk_cnt[4].ENA
can_data_clk => clk_cnt[3].ENA
can_data_clk => clk_cnt[2].ENA
can_data_clk => clk_cnt[1].ENA
can_data_clk => clk_cnt[0].ENA
can_data_clk => clk_cnt[9].ENA
data_clk <= t_clk.DB_MAX_OUTPUT_PORT_TYPE


|cpu|read_return_pre_set:u_rx_tx|tx16:u_tx
rst => data_clk:u_data_clk.rst
rst => t_tx~2.OUTPUTSELECT
rst => process1~0.IN0
rst => process0~0.IN0
p1mhz => data_clk:u_data_clk.p1mhz
data_in[0] => Mux~0.IN15
data_in[1] => Mux~0.IN14
data_in[2] => Mux~0.IN13
data_in[3] => Mux~0.IN12
data_in[4] => Mux~0.IN11
data_in[5] => Mux~0.IN10
data_in[6] => Mux~0.IN9
data_in[7] => Mux~0.IN8
data_in[8] => Mux~0.IN7
data_in[9] => Mux~0.IN6
data_in[10] => Mux~0.IN5
data_in[11] => Mux~0.IN4
data_in[12] => Mux~0.IN3
data_in[13] => Mux~0.IN2
data_in[14] => Mux~0.IN1
data_in[15] => Mux~0.IN0
tx <= t_tx~2.DB_MAX_OUTPUT_PORT_TYPE
start_tx => en_tx.CLK
on_tx <= en_tx.DB_MAX_OUTPUT_PORT_TYPE


|cpu|read_return_pre_set:u_rx_tx|tx16:u_tx|data_clk:u_data_clk
rst => gen_clk~0.IN1
p1mhz => clk_cnt[8].CLK
p1mhz => clk_cnt[7].CLK
p1mhz => clk_cnt[6].CLK
p1mhz => clk_cnt[5].CLK
p1mhz => clk_cnt[4].CLK
p1mhz => clk_cnt[3].CLK
p1mhz => clk_cnt[2].CLK
p1mhz => clk_cnt[1].CLK
p1mhz => clk_cnt[0].CLK
p1mhz => t_clk.CLK
p1mhz => clk_cnt[9].CLK
can_data_clk => gen_clk~0.IN0
can_data_clk => clk_cnt[8].ENA
can_data_clk => clk_cnt[7].ENA
can_data_clk => clk_cnt[6].ENA
can_data_clk => clk_cnt[5].ENA
can_data_clk => clk_cnt[4].ENA
can_data_clk => clk_cnt[3].ENA
can_data_clk => clk_cnt[2].ENA
can_data_clk => clk_cnt[1].ENA
can_data_clk => clk_cnt[0].ENA
can_data_clk => clk_cnt[9].ENA
data_clk <= t_clk.DB_MAX_OUTPUT_PORT_TYPE


|cpu|time_out:u_time_out
rst => y7b_time_cnt~0.IN1
rst => sec1_time_cnt~0.IN0
rst => setup_sec1_time_out_tag~0.IN0
rst => setup_y7b_time_out_tag~0.IN0
sa[0] => reduce_nor~3.IN12
sa[0] => reduce_nor~0.IN12
sa[1] => reduce_nor~0.IN11
sa[1] => reduce_nor~3.IN11
sa[2] => reduce_nor~3.IN13
sa[2] => reduce_nor~0.IN13
sa[3] => reduce_nor~0.IN10
sa[3] => reduce_nor~3.IN10
sa[4] => reduce_nor~0.IN9
sa[4] => reduce_nor~3.IN9
sa[5] => reduce_nor~0.IN8
sa[5] => reduce_nor~3.IN8
sa[6] => reduce_nor~0.IN7
sa[6] => reduce_nor~3.IN7
sa[7] => reduce_nor~0.IN6
sa[7] => reduce_nor~3.IN6
sa[8] => reduce_nor~0.IN5
sa[8] => reduce_nor~3.IN5
sa[9] => reduce_nor~0.IN4
sa[9] => reduce_nor~3.IN4
sa[10] => reduce_nor~0.IN3
sa[10] => reduce_nor~3.IN3
sa[11] => reduce_nor~0.IN2
sa[11] => reduce_nor~3.IN2
sa[12] => reduce_nor~0.IN1
sa[12] => reduce_nor~3.IN1
sa[13] => reduce_nor~0.IN0
sa[13] => reduce_nor~3.IN0
sa[14] => reduce_nor~0.IN14
sa[14] => reduce_nor~3.IN14
sa[15] => reduce_nor~0.IN15
sa[15] => reduce_nor~3.IN15
iow => sec1_tag.CLK
iow => Y7B_tag.CLK
iow => y7b_time_cnt~1.IN1
iow => sec1_time_cnt~1.IN0
ad_in[0] => reduce_nor~4.IN6
ad_in[1] => reduce_nor~4.IN5
ad_in[2] => reduce_nor~4.IN4
ad_in[3] => reduce_nor~4.IN3
ad_in[4] => setup_y7b_time_out_tag~2.IN1
ad_in[4] => reduce_nor~1.IN1
ad_in[4] => reduce_nor~4.IN1
ad_in[5] => setup_y7b_time_out_tag~2.IN0
ad_in[5] => reduce_nor~1.IN0
ad_in[5] => reduce_nor~4.IN0
ad_in[6] => reduce_nor~4.IN2
ad_in[7] => reduce_nor~4.IN7
p1khz => y7b_time_out_tag[6]~reg0.CLK
p1khz => y7b_time_out_tag[5]~reg0.CLK
p1khz => y7b_time_out_tag[4]~reg0.CLK
p1khz => y7b_time_out_tag[3]~reg0.CLK
p1khz => y7b_time_out_tag[2]~reg0.CLK
p1khz => y7b_time_out_tag[1]~reg0.CLK
p1khz => y7b_time_out_tag[0]~reg0.CLK
p1khz => y7b_time_out_cnt[10].CLK
p1khz => y7b_time_out_cnt[9].CLK