p1khz => y7b_time_out_cnt[8].CLK
p1khz => y7b_time_out_cnt[7].CLK
p1khz => y7b_time_out_cnt[6].CLK
p1khz => y7b_time_out_cnt[5].CLK
p1khz => y7b_time_out_cnt[4].CLK
p1khz => y7b_time_out_cnt[3].CLK
p1khz => y7b_time_out_cnt[2].CLK
p1khz => y7b_time_out_cnt[1].CLK
p1khz => y7b_time_out_cnt[0].CLK
p1khz => y7b_end_tag.CLK
p1khz => sec1_time_out_tag[7]~reg0.CLK
p1khz => sec1_time_out_tag[6]~reg0.CLK
p1khz => sec1_time_out_tag[5]~reg0.CLK
p1khz => sec1_time_out_tag[4]~reg0.CLK
p1khz => sec1_time_out_tag[3]~reg0.CLK
p1khz => sec1_time_out_tag[2]~reg0.CLK
p1khz => sec1_time_out_tag[1]~reg0.CLK
p1khz => sec1_time_out_tag[0]~reg0.CLK
p1khz => sec1_time_out_cnt[9].CLK
p1khz => sec1_time_out_cnt[8].CLK
p1khz => sec1_time_out_cnt[7].CLK
p1khz => sec1_time_out_cnt[6].CLK
p1khz => sec1_time_out_cnt[5].CLK
p1khz => sec1_time_out_cnt[4].CLK
p1khz => sec1_time_out_cnt[3].CLK
p1khz => sec1_time_out_cnt[2].CLK
p1khz => sec1_time_out_cnt[1].CLK
p1khz => sec1_time_out_cnt[0].CLK
p1khz => sec1_end_tag.CLK
p1khz => y7b_time_out_tag[7]~reg0.CLK
y7b_time_out_tag[0] <= y7b_time_out_tag[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
y7b_time_out_tag[1] <= y7b_time_out_tag[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
y7b_time_out_tag[2] <= y7b_time_out_tag[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
y7b_time_out_tag[3] <= y7b_time_out_tag[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
y7b_time_out_tag[4] <= y7b_time_out_tag[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
y7b_time_out_tag[5] <= y7b_time_out_tag[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
y7b_time_out_tag[6] <= y7b_time_out_tag[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
y7b_time_out_tag[7] <= y7b_time_out_tag[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec1_time_out_tag[0] <= sec1_time_out_tag[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec1_time_out_tag[1] <= sec1_time_out_tag[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec1_time_out_tag[2] <= sec1_time_out_tag[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec1_time_out_tag[3] <= sec1_time_out_tag[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec1_time_out_tag[4] <= sec1_time_out_tag[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec1_time_out_tag[5] <= sec1_time_out_tag[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec1_time_out_tag[6] <= sec1_time_out_tag[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec1_time_out_tag[7] <= sec1_time_out_tag[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|generate_int:u_int
rst => wri_reg8:u_com.rst
rst => cnt_urgency_put_tag~0.IN0
rst => setup_ready_reset_tag~0.IN0
rst => cnt_ready_reset_tag~0.IN0
rst => setup_urgency_put_tag~0.IN0
p1mhz => ~NO_FANOUT~
urgency_put_opt_in => urgency_put_opt_inx~2.IN0
urgency_put_opt_in => urgency_put_tag.CLK
ready_reset_opt_in => ready_reset_opt_inx~2.IN0
ready_reset_opt_in => ready_reset_tag.CLK
urgency_put_opt_inx <= urgency_put_opt_inx~2.DB_MAX_OUTPUT_PORT_TYPE
ready_reset_opt_inx <= ready_reset_opt_inx~2.DB_MAX_OUTPUT_PORT_TYPE
sa[0] => reduce_nor~0.IN11
sa[1] => reduce_nor~0.IN12
sa[2] => reduce_nor~0.IN13
sa[3] => reduce_nor~0.IN10
sa[4] => reduce_nor~0.IN9
sa[5] => reduce_nor~0.IN8
sa[6] => reduce_nor~0.IN7
sa[7] => reduce_nor~0.IN6
sa[8] => reduce_nor~0.IN5
sa[9] => reduce_nor~0.IN4
sa[10] => reduce_nor~0.IN3
sa[11] => reduce_nor~0.IN2
sa[12] => reduce_nor~0.IN1
sa[13] => reduce_nor~0.IN0
sa[14] => reduce_nor~0.IN14
sa[15] => reduce_nor~0.IN15
iow => wri_reg8:u_com.iow
ad_in[0] => wri_reg8:u_com.data_in[0]
ad_in[1] => wri_reg8:u_com.data_in[1]
ad_in[2] => wri_reg8:u_com.data_in[2]
ad_in[3] => wri_reg8:u_com.data_in[3]
ad_in[4] => wri_reg8:u_com.data_in[4]
ad_in[5] => wri_reg8:u_com.data_in[5]
ad_in[6] => wri_reg8:u_com.data_in[6]
ad_in[7] => wri_reg8:u_com.data_in[7]
p1khz => cnt_urgency_put[4].CLK
p1khz => cnt_urgency_put[3].CLK
p1khz => cnt_urgency_put[2].CLK
p1khz => cnt_urgency_put[1].CLK
p1khz => cnt_urgency_put[0].CLK
p1khz => urgency_put_tag_end.CLK
p1khz => cnt_urgency_put[5].CLK
p1khz => cnt_ready_reset[4].CLK
p1khz => cnt_ready_reset[3].CLK
p1khz => cnt_ready_reset[2].CLK
p1khz => cnt_ready_reset[1].CLK
p1khz => cnt_ready_reset[0].CLK
p1khz => ready_reset_tag_end.CLK
p1khz => cnt_ready_reset[5].CLK


|cpu|generate_int:u_int|wri_reg8:u_com
iow => data_out[6]~reg0.CLK
iow => data_out[5]~reg0.CLK
iow => data_out[4]~reg0.CLK
iow => data_out[3]~reg0.CLK
iow => data_out[2]~reg0.CLK
iow => data_out[1]~reg0.CLK
iow => data_out[0]~reg0.CLK
iow => data_out[7]~reg0.CLK
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
cs => data_out[6]~reg0.ENA
cs => data_out[5]~reg0.ENA
cs => data_out[4]~reg0.ENA
cs => data_out[3]~reg0.ENA
cs => data_out[2]~reg0.ENA
cs => data_out[1]~reg0.ENA
cs => data_out[0]~reg0.ENA
cs => data_out[7]~reg0.ENA
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|timer:U_TIMER
rst => t_60s_cnt[4].ACLR
rst => t_60s_cnt[3].ACLR
rst => t_60s_cnt[2].ACLR
rst => t_60s_cnt[1].ACLR
rst => t_60s_cnt[0].ACLR
rst => t_60s.ACLR
rst => t_60min_cnt[4].ACLR
rst => t_60s_cnt[5].ACLR
rst => t_60min_cnt[3].ACLR
rst => t_60min_cnt[2].ACLR
rst => t_60min_cnt[1].ACLR
rst => t_60min_cnt[0].ACLR
rst => t_60min.ACLR
rst => t_60min_cnt[5].ACLR
rst => t_hour_cnt[5].ACLR
rst => t_hour_cnt[4].ACLR
rst => t_hour_cnt[3].ACLR
rst => t_hour_cnt[2].ACLR
rst => t_hour_cnt[1].ACLR
rst => t_hour_cnt[0].ACLR
rst => t_hour_cnt[6].ACLR
p1khz => t_1s_cnt[7].CLK
p1khz => t_1s_cnt[6].CLK
p1khz => t_1s_cnt[5].CLK
p1khz => t_1s_cnt[4].CLK
p1khz => t_1s_cnt[3].CLK
p1khz => t_1s_cnt[2].CLK
p1khz => t_1s_cnt[1].CLK
p1khz => t_1s_cnt[0].CLK
p1khz => t_1s.CLK
p1khz => t_1s_cnt[8].CLK
sec[0] <= t_60s_cnt[0].DB_MAX_OUTPUT_PORT_TYPE
sec[1] <= t_60s_cnt[1].DB_MAX_OUTPUT_PORT_TYPE
sec[2] <= t_60s_cnt[2].DB_MAX_OUTPUT_PORT_TYPE
sec[3] <= t_60s_cnt[3].DB_MAX_OUTPUT_PORT_TYPE
sec[4] <= t_60s_cnt[4].DB_MAX_OUTPUT_PORT_TYPE
sec[5] <= t_60s_cnt[5].DB_MAX_OUTPUT_PORT_TYPE
sec[6] <= <GND>
sec[7] <= <GND>
min[0] <= t_60min_cnt[0].DB_MAX_OUTPUT_PORT_TYPE
min[1] <= t_60min_cnt[1].DB_MAX_OUTPUT_PORT_TYPE
min[2] <= t_60min_cnt[2].DB_MAX_OUTPUT_PORT_TYPE
min[3] <= t_60min_cnt[3].DB_MAX_OUTPUT_PORT_TYPE
min[4] <= t_60min_cnt[4].DB_MAX_OUTPUT_PORT_TYPE
min[5] <= t_60min_cnt[5].DB_MAX_OUTPUT_PORT_TYPE
min[6] <= <GND>
min[7] <= <GND>
hour[0] <= t_hour_cnt[0].DB_MAX_OUTPUT_PORT_TYPE
hour[1] <= t_hour_cnt[1].DB_MAX_OUTPUT_PORT_TYPE
hour[2] <= t_hour_cnt[2].DB_MAX_OUTPUT_PORT_TYPE
hour[3] <= t_hour_cnt[3].DB_MAX_OUTPUT_PORT_TYPE
hour[4] <= t_hour_cnt[4].DB_MAX_OUTPUT_PORT_TYPE
hour[5] <= t_hour_cnt[5].DB_MAX_OUTPUT_PORT_TYPE
hour[6] <= t_hour_cnt[6].DB_MAX_OUTPUT_PORT_TYPE
hour[7] <= <GND>


|cpu|tx8:u_tx8
rst => data_clk:u_data_clk.rst
rst => wri_reg8:u_write_data.rst
rst => t_tx~2.OUTPUTSELECT
rst => process1~0.IN0
rst => process0~0.IN0
p1mhz => data_clk:u_data_clk.p1mhz
sa[0] => reduce_nor~0.IN11
sa[0] => reduce_nor~1.IN11
sa[1] => reduce_nor~0.IN12
sa[1] => reduce_nor~1.IN12
sa[2] => reduce_nor~0.IN10
sa[2] => reduce_nor~1.IN10
sa[3] => reduce_nor~0.IN13
sa[3] => reduce_nor~1.IN13
sa[4] => reduce_nor~0.IN9
sa[4] => reduce_nor~1.IN9
sa[5] => reduce_nor~0.IN8
sa[5] => reduce_nor~1.IN8
sa[6] => reduce_nor~0.IN7
sa[6] => reduce_nor~1.IN7
sa[7] => reduce_nor~0.IN6
sa[7] => reduce_nor~1.IN6
sa[8] => reduce_nor~0.IN5
sa[8] => reduce_nor~1.IN5
sa[9] => reduce_nor~0.IN4
sa[9] => reduce_nor~1.IN4
sa[10] => reduce_nor~0.IN3
sa[10] => reduce_nor~1.IN3
sa[11] => reduce_nor~0.IN2
sa[11] => reduce_nor~1.IN2
sa[12] => reduce_nor~0.IN1
sa[12] => reduce_nor~1.IN1
sa[13] => reduce_nor~0.IN0
sa[13] => reduce_nor~1.IN0
sa[14] => reduce_nor~0.IN14
sa[14] => reduce_nor~1.IN14
sa[15] => reduce_nor~0.IN15
sa[15] => reduce_nor~1.IN15
ad_in[0] => wri_reg8:u_write_data.data_in[0]
ad_in[1] => wri_reg8:u_write_data.data_in[1]
ad_in[2] => wri_reg8:u_write_data.data_in[2]
ad_in[3] => wri_reg8:u_write_data.data_in[3]
ad_in[4] => wri_reg8:u_write_data.data_in[4]
ad_in[5] => wri_reg8:u_write_data.data_in[5]
ad_in[6] => wri_reg8:u_write_data.data_in[6]
ad_in[7] => wri_reg8:u_write_data.data_in[7]
iow => wri_reg8:u_write_data.iow
iow => en_tx.CLK
tx <= t_tx~2.DB_MAX_OUTPUT_PORT_TYPE
on_tx <= en_tx.DB_MAX_OUTPUT_PORT_TYPE


|cpu|tx8:u_tx8|wri_reg8:u_write_data
iow => data_out[6]~reg0.CLK
iow => data_out[5]~reg0.CLK
iow => data_out[4]~reg0.CLK
iow => data_out[3]~reg0.CLK
iow => data_out[2]~reg0.CLK
iow => data_out[1]~reg0.CLK
iow => data_out[0]~reg0.CLK
iow => data_out[7]~reg0.CLK
rst => data_out[6]~reg0.ACLR
rst => data_out[5]~reg0.ACLR
rst => data_out[4]~reg0.ACLR
rst => data_out[3]~reg0.ACLR
rst => data_out[2]~reg0.ACLR
rst => data_out[1]~reg0.ACLR
rst => data_out[0]~reg0.ACLR
rst => data_out[7]~reg0.ACLR
cs => data_out[6]~reg0.ENA
cs => data_out[5]~reg0.ENA
cs => data_out[4]~reg0.ENA
cs => data_out[3]~reg0.ENA
cs => data_out[2]~reg0.ENA
cs => data_out[1]~reg0.ENA
cs => data_out[0]~reg0.ENA
cs => data_out[7]~reg0.ENA
data_in[0] => data_out[0]~reg0.DATAIN
data_in[1] => data_out[1]~reg0.DATAIN
data_in[2] => data_out[2]~reg0.DATAIN
data_in[3] => data_out[3]~reg0.DATAIN
data_in[4] => data_out[4]~reg0.DATAIN
data_in[5] => data_out[5]~reg0.DATAIN
data_in[6] => data_out[6]~reg0.DATAIN
data_in[7] => data_out[7]~reg0.DATAIN
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|tx8:u_tx8|data_clk:u_data_clk
rst => gen_clk~0.IN1
p1mhz => clk_cnt[8].CLK
p1mhz => clk_cnt[7].CLK
p1mhz => clk_cnt[6].CLK
p1mhz => clk_cnt[5].CLK
p1mhz => clk_cnt[4].CLK
p1mhz => clk_cnt[3].CLK
p1mhz => clk_cnt[2].CLK
p1mhz => clk_cnt[1].CLK
p1mhz => clk_cnt[0].CLK
p1mhz => t_clk.CLK
p1mhz => clk_cnt[9].CLK
can_data_clk => gen_clk~0.IN0
can_data_clk => clk_cnt[8].ENA
can_data_clk => clk_cnt[7].ENA
can_data_clk => clk_cnt[6].ENA
can_data_clk => clk_cnt[5].ENA
can_data_clk => clk_cnt[4].ENA
can_data_clk => clk_cnt[3].ENA
can_data_clk => clk_cnt[2].ENA
can_data_clk => clk_cnt[1].ENA
can_data_clk => clk_cnt[0].ENA
can_data_clk => clk_cnt[9].ENA
data_clk <= t_clk.DB_MAX_OUTPUT_PORT_TYPE


|cpu|rx8:u_rx8
rst => data_clk:u_data_clk.rst
rst => t_data[10].ACLR
rst => process0~1.IN0
rst => t_data[8].ACLR
rst => t_data[7].ACLR
rst => t_data[6].ACLR
rst => t_data[5].ACLR
rst => t_data[4].ACLR
rst => t_data[3].ACLR
rst => t_data[2].ACLR
rst => t_data[1].ACLR
rst => t_data[0].ACLR
rst => stup_en_rx~0.IN0
rst => gen_write_data_cnt~0.IN0
p1mhz => data_clk:u_data_clk.p1mhz
rx => Mux~0.IN6
rx => Mux~1.IN4
rx => Mux~2.IN11
rx => Mux~3.IN10
rx => Mux~4.IN9
rx => Mux~5.IN8
rx => Mux~6.IN7
rx => Mux~7.IN6
rx => Mux~8.IN5
rx => Mux~9.IN4
rx => en_rx.CLK
data_out[0] <= t_data[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= t_data[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= t_data[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= t_data[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= t_data[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= t_data[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= t_data[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= t_data[8].DB_MAX_OUTPUT_PORT_TYPE
rx_tag <= t_rx_tag.DB_MAX_OUTPUT_PORT_TYPE
SA[0] => reduce_nor~1.IN12
SA[1] => reduce_nor~1.IN11
SA[2] => reduce_nor~1.IN10
SA[3] => reduce_nor~1.IN9
SA[4] => reduce_nor~1.IN8
SA[5] => reduce_nor~1.IN13
SA[6] => reduce_nor~1.IN7
SA[7] => reduce_nor~1.IN6
SA[8] => reduce_nor~1.IN5
SA[9] => reduce_nor~1.IN4
SA[10] => reduce_nor~1.IN3
SA[11] => reduce_nor~1.IN2
SA[12] => reduce_nor~1.IN1
SA[13] => reduce_nor~1.IN0
SA[14] => reduce_nor~1.IN14
SA[15] => reduce_nor~1.IN15
ior => process0~0.IN1


|cpu|rx8:u_rx8|data_clk:u_data_clk
rst => gen_clk~0.IN1
p1mhz => clk_cnt[8].CLK
p1mhz => clk_cnt[7].CLK
p1mhz => clk_cnt[6].CLK
p1mhz => clk_cnt[5].CLK
p1mhz => clk_cnt[4].CLK
p1mhz => clk_cnt[3].CLK
p1mhz => clk_cnt[2].CLK
p1mhz => clk_cnt[1].CLK
p1mhz => clk_cnt[0].CLK
p1mhz => t_clk.CLK
p1mhz => clk_cnt[9].CLK
can_data_clk => gen_clk~0.IN0
can_data_clk => clk_cnt[8].ENA
can_data_clk => clk_cnt[7].ENA
can_data_clk => clk_cnt[6].ENA
can_data_clk => clk_cnt[5].ENA
can_data_clk => clk_cnt[4].ENA
can_data_clk => clk_cnt[3].ENA
can_data_clk => clk_cnt[2].ENA
can_data_clk => clk_cnt[1].ENA
can_data_clk => clk_cnt[0].ENA
can_data_clk => clk_cnt[9].ENA
data_clk <= t_clk.DB_MAX_OUTPUT_PORT_TYPE