?? lcdfinal.fit.rpt
字號:
Fitter report for lcdfinal
Tue Mar 31 16:07:07 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Partition Preservation Settings
5. Pin-Out File
6. Fitter Resource Usage Summary
7. Input Pins
8. Output Pins
9. Bidir Pins
10. I/O Bank Usage
11. All Package Pins
12. Output Pin Default Load For Reported TCO
13. Fitter Resource Utilization by Entity
14. Delay Chain Summary
15. Pad To Core Delay Chain Fanout
16. Control Signals
17. Global & Other Fast Signals
18. Non-Global High Fan-Out Signals
19. Interconnect Usage Summary
20. LAB Logic Elements
21. LAB-wide Signals
22. LAB Signals Sourced
23. LAB Signals Sourced Out
24. LAB Distinct Inputs
25. Fitter Device Options
26. Operating Settings and Conditions
27. Advanced Data - General
28. Advanced Data - Placement Preparation
29. Advanced Data - Placement
30. Advanced Data - Routing
31. Fitter Messages
32. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+------------------------------------------+
; Fitter Status ; Successful - Tue Mar 31 16:07:07 2009 ;
; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name ; lcdfinal ;
; Top-level Entity Name ; lcdfinal ;
; Family ; Cyclone II ;
; Device ; EP2C35F672C6 ;
; Timing Models ; Final ;
; Total logic elements ; 377 / 33,216 ( 1 % ) ;
; Total combinational functions ; 340 / 33,216 ( 1 % ) ;
; Dedicated logic registers ; 186 / 33,216 ( < 1 % ) ;
; Total registers ; 186 ;
; Total pins ; 93 / 475 ( 20 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 483,840 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
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