?? prev_cmp_lcdfinal.tan.qmsg
字號:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register passed_lock:p0\|next_sub_state.first_633 register passed_lock:p0\|sub_state.first 106.81 MHz 9.362 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 106.81 MHz between source register \"passed_lock:p0\|next_sub_state.first_633\" and destination register \"passed_lock:p0\|sub_state.first\" (period= 9.362 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.485 ns + Longest register register " "Info: + Longest register to register delay is 0.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns passed_lock:p0\|next_sub_state.first_633 1 REG LCCOMB_X21_Y18_N22 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X21_Y18_N22; Fanout = 1; REG Node = 'passed_lock:p0\|next_sub_state.first_633'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.251 ns) + CELL(0.150 ns) 0.401 ns passed_lock:p0\|sub_state.first~8 2 COMB LCCOMB_X21_Y18_N26 1 " "Info: 2: + IC(0.251 ns) + CELL(0.150 ns) = 0.401 ns; Loc. = LCCOMB_X21_Y18_N26; Fanout = 1; COMB Node = 'passed_lock:p0\|sub_state.first~8'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.401 ns" { passed_lock:p0|next_sub_state.first_633 passed_lock:p0|sub_state.first~8 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.485 ns passed_lock:p0\|sub_state.first 3 REG LCFF_X21_Y18_N27 4 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.485 ns; Loc. = LCFF_X21_Y18_N27; Fanout = 4; REG Node = 'passed_lock:p0\|sub_state.first'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { passed_lock:p0|sub_state.first~8 passed_lock:p0|sub_state.first } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.234 ns ( 48.25 % ) " "Info: Total cell delay = 0.234 ns ( 48.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.251 ns ( 51.75 % ) " "Info: Total interconnect delay = 0.251 ns ( 51.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.485 ns" { passed_lock:p0|next_sub_state.first_633 passed_lock:p0|sub_state.first~8 passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.485 ns" { passed_lock:p0|next_sub_state.first_633 {} passed_lock:p0|sub_state.first~8 {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.251ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.232 ns - Smallest " "Info: - Smallest clock skew is -4.232 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.689 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.689 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 179 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 179; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.035 ns) + CELL(0.537 ns) 2.689 ns passed_lock:p0\|sub_state.first 3 REG LCFF_X21_Y18_N27 4 " "Info: 3: + IC(1.035 ns) + CELL(0.537 ns) = 2.689 ns; Loc. = LCFF_X21_Y18_N27; Fanout = 4; REG Node = 'passed_lock:p0\|sub_state.first'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.12 % ) " "Info: Total cell delay = 1.536 ns ( 57.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.153 ns ( 42.88 % ) " "Info: Total interconnect delay = 1.153 ns ( 42.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.689 ns" { CLOCK_50 CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.689 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.000ns 0.118ns 1.035ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 6.921 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 6.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 2.800 ns cmd\[2\] 2 REG LCFF_X20_Y18_N29 7 " "Info: 2: + IC(1.014 ns) + CELL(0.787 ns) = 2.800 ns; Loc. = LCFF_X20_Y18_N29; Fanout = 7; REG Node = 'cmd\[2\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.801 ns" { CLOCK_50 cmd[2] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.545 ns) + CELL(0.438 ns) 3.783 ns passed_lock:p0\|next_sub_state.finish~2 3 COMB LCCOMB_X20_Y18_N16 1 " "Info: 3: + IC(0.545 ns) + CELL(0.438 ns) = 3.783 ns; Loc. = LCCOMB_X20_Y18_N16; Fanout = 1; COMB Node = 'passed_lock:p0\|next_sub_state.finish~2'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.983 ns" { cmd[2] passed_lock:p0|next_sub_state.finish~2 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.598 ns) + CELL(0.000 ns) 5.381 ns passed_lock:p0\|next_sub_state.finish~2clkctrl 4 COMB CLKCTRL_G1 5 " "Info: 4: + IC(1.598 ns) + CELL(0.000 ns) = 5.381 ns; Loc. = CLKCTRL_G1; Fanout = 5; COMB Node = 'passed_lock:p0\|next_sub_state.finish~2clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.390 ns) + CELL(0.150 ns) 6.921 ns passed_lock:p0\|next_sub_state.first_633 5 REG LCCOMB_X21_Y18_N22 1 " "Info: 5: + IC(1.390 ns) + CELL(0.150 ns) = 6.921 ns; Loc. = LCCOMB_X21_Y18_N22; Fanout = 1; REG Node = 'passed_lock:p0\|next_sub_state.first_633'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.540 ns" { passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.374 ns ( 34.30 % ) " "Info: Total cell delay = 2.374 ns ( 34.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.547 ns ( 65.70 % ) " "Info: Total interconnect delay = 4.547 ns ( 65.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.921 ns" { CLOCK_50 cmd[2] passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.921 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[2] {} passed_lock:p0|next_sub_state.finish~2 {} passed_lock:p0|next_sub_state.finish~2clkctrl {} passed_lock:p0|next_sub_state.first_633 {} } { 0.000ns 0.000ns 1.014ns 0.545ns 1.598ns 1.390ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.689 ns" { CLOCK_50 CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.689 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.000ns 0.118ns 1.035ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.921 ns" { CLOCK_50 cmd[2] passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.921 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[2] {} passed_lock:p0|next_sub_state.finish~2 {} passed_lock:p0|next_sub_state.finish~2clkctrl {} passed_lock:p0|next_sub_state.first_633 {} } { 0.000ns 0.000ns 1.014ns 0.545ns 1.598ns 1.390ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.485 ns" { passed_lock:p0|next_sub_state.first_633 passed_lock:p0|sub_state.first~8 passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.485 ns" { passed_lock:p0|next_sub_state.first_633 {} passed_lock:p0|sub_state.first~8 {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.251ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.689 ns" { CLOCK_50 CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.689 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.000ns 0.118ns 1.035ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.921 ns" { CLOCK_50 cmd[2] passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.921 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[2] {} passed_lock:p0|next_sub_state.finish~2 {} passed_lock:p0|next_sub_state.finish~2clkctrl {} passed_lock:p0|next_sub_state.first_633 {} } { 0.000ns 0.000ns 1.014ns 0.545ns 1.598ns 1.390ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLOCK_50 109 " "Warning: Circuit may not operate. Detected 109 non-operational path(s) clocked by clock \"CLOCK_50\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "passed_lock:p0\|sub_state.first passed_lock:p0\|next_sub_state.first_633 CLOCK_50 2.994 ns " "Info: Found hold time violation between source pin or register \"passed_lock:p0\|sub_state.first\" and destination pin or register \"passed_lock:p0\|next_sub_state.first_633\" for clock \"CLOCK_50\" (Hold time is 2.994 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.232 ns + Largest " "Info: + Largest clock skew is 4.232 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 6.921 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 6.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.787 ns) 2.800 ns cmd\[2\] 2 REG LCFF_X20_Y18_N29 7 " "Info: 2: + IC(1.014 ns) + CELL(0.787 ns) = 2.800 ns; Loc. = LCFF_X20_Y18_N29; Fanout = 7; REG Node = 'cmd\[2\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.801 ns" { CLOCK_50 cmd[2] } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 74 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.545 ns) + CELL(0.438 ns) 3.783 ns passed_lock:p0\|next_sub_state.finish~2 3 COMB LCCOMB_X20_Y18_N16 1 " "Info: 3: + IC(0.545 ns) + CELL(0.438 ns) = 3.783 ns; Loc. = LCCOMB_X20_Y18_N16; Fanout = 1; COMB Node = 'passed_lock:p0\|next_sub_state.finish~2'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.983 ns" { cmd[2] passed_lock:p0|next_sub_state.finish~2 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.598 ns) + CELL(0.000 ns) 5.381 ns passed_lock:p0\|next_sub_state.finish~2clkctrl 4 COMB CLKCTRL_G1 5 " "Info: 4: + IC(1.598 ns) + CELL(0.000 ns) = 5.381 ns; Loc. = CLKCTRL_G1; Fanout = 5; COMB Node = 'passed_lock:p0\|next_sub_state.finish~2clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.390 ns) + CELL(0.150 ns) 6.921 ns passed_lock:p0\|next_sub_state.first_633 5 REG LCCOMB_X21_Y18_N22 1 " "Info: 5: + IC(1.390 ns) + CELL(0.150 ns) = 6.921 ns; Loc. = LCCOMB_X21_Y18_N22; Fanout = 1; REG Node = 'passed_lock:p0\|next_sub_state.first_633'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.540 ns" { passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.374 ns ( 34.30 % ) " "Info: Total cell delay = 2.374 ns ( 34.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.547 ns ( 65.70 % ) " "Info: Total interconnect delay = 4.547 ns ( 65.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.921 ns" { CLOCK_50 cmd[2] passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.921 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[2] {} passed_lock:p0|next_sub_state.finish~2 {} passed_lock:p0|next_sub_state.finish~2clkctrl {} passed_lock:p0|next_sub_state.first_633 {} } { 0.000ns 0.000ns 1.014ns 0.545ns 1.598ns 1.390ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.689 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to source register is 2.689 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 8; CLK Node = 'CLOCK_50'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 179 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 179; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "lcdfinal.v" "" { Text "F:/jeffie/final/STATE2/lcdfinal.v" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.035 ns) + CELL(0.537 ns) 2.689 ns passed_lock:p0\|sub_state.first 3 REG LCFF_X21_Y18_N27 4 " "Info: 3: + IC(1.035 ns) + CELL(0.537 ns) = 2.689 ns; Loc. = LCFF_X21_Y18_N27; Fanout = 4; REG Node = 'passed_lock:p0\|sub_state.first'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.12 % ) " "Info: Total cell delay = 1.536 ns ( 57.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.153 ns ( 42.88 % ) " "Info: Total interconnect delay = 1.153 ns ( 42.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.689 ns" { CLOCK_50 CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.689 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.000ns 0.118ns 1.035ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.921 ns" { CLOCK_50 cmd[2] passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.921 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[2] {} passed_lock:p0|next_sub_state.finish~2 {} passed_lock:p0|next_sub_state.finish~2clkctrl {} passed_lock:p0|next_sub_state.first_633 {} } { 0.000ns 0.000ns 1.014ns 0.545ns 1.598ns 1.390ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.689 ns" { CLOCK_50 CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.689 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.000ns 0.118ns 1.035ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.988 ns - Shortest register register " "Info: - Shortest register to register delay is 0.988 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns passed_lock:p0\|sub_state.first 1 REG LCFF_X21_Y18_N27 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y18_N27; Fanout = 4; REG Node = 'passed_lock:p0\|sub_state.first'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { passed_lock:p0|sub_state.first } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.323 ns) + CELL(0.150 ns) 0.473 ns passed_lock:p0\|next_sub_state.first~76 2 COMB LCCOMB_X21_Y18_N24 1 " "Info: 2: + IC(0.323 ns) + CELL(0.150 ns) = 0.473 ns; Loc. = LCCOMB_X21_Y18_N24; Fanout = 1; COMB Node = 'passed_lock:p0\|next_sub_state.first~76'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.473 ns" { passed_lock:p0|sub_state.first passed_lock:p0|next_sub_state.first~76 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.244 ns) + CELL(0.271 ns) 0.988 ns passed_lock:p0\|next_sub_state.first_633 3 REG LCCOMB_X21_Y18_N22 1 " "Info: 3: + IC(0.244 ns) + CELL(0.271 ns) = 0.988 ns; Loc. = LCCOMB_X21_Y18_N22; Fanout = 1; REG Node = 'passed_lock:p0\|next_sub_state.first_633'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.515 ns" { passed_lock:p0|next_sub_state.first~76 passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.421 ns ( 42.61 % ) " "Info: Total cell delay = 0.421 ns ( 42.61 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.567 ns ( 57.39 % ) " "Info: Total interconnect delay = 0.567 ns ( 57.39 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.988 ns" { passed_lock:p0|sub_state.first passed_lock:p0|next_sub_state.first~76 passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.988 ns" { passed_lock:p0|sub_state.first {} passed_lock:p0|next_sub_state.first~76 {} passed_lock:p0|next_sub_state.first_633 {} } { 0.000ns 0.323ns 0.244ns } { 0.000ns 0.150ns 0.271ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" { } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 56 -1 0 } } { "passed_lock.v" "" { Text "F:/jeffie/final/STATE2/passed_lock.v" 232 0 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.921 ns" { CLOCK_50 cmd[2] passed_lock:p0|next_sub_state.finish~2 passed_lock:p0|next_sub_state.finish~2clkctrl passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.921 ns" { CLOCK_50 {} CLOCK_50~combout {} cmd[2] {} passed_lock:p0|next_sub_state.finish~2 {} passed_lock:p0|next_sub_state.finish~2clkctrl {} passed_lock:p0|next_sub_state.first_633 {} } { 0.000ns 0.000ns 1.014ns 0.545ns 1.598ns 1.390ns } { 0.000ns 0.999ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.689 ns" { CLOCK_50 CLOCK_50~clkctrl passed_lock:p0|sub_state.first } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.689 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} passed_lock:p0|sub_state.first {} } { 0.000ns 0.000ns 0.118ns 1.035ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.988 ns" { passed_lock:p0|sub_state.first passed_lock:p0|next_sub_state.first~76 passed_lock:p0|next_sub_state.first_633 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.988 ns" { passed_lock:p0|sub_state.first {} passed_lock:p0|next_sub_state.first~76 {} passed_lock:p0|next_sub_state.first_633 {} } { 0.000ns 0.323ns 0.244ns } { 0.000ns 0.150ns 0.271ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}
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