-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

-- DATE "12/05/2008 22:04:57"

-- 
-- Device: Altera EP2C5Q208C8 Package PQFP208
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	DDS IS
    PORT (
	K : IN std_logic_vector(9 DOWNTO 0);
	EN : IN std_logic;
	RESET : IN std_logic;
	CLK : IN std_logic;
	Q : OUT std_logic_vector(8 DOWNTO 0)
	);
END DDS;

ARCHITECTURE structure OF DDS IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_K : std_logic_vector(9 DOWNTO 0);
SIGNAL ww_EN : std_logic;
SIGNAL ww_RESET : std_logic;
SIGNAL ww_CLK : std_logic;
SIGNAL ww_Q : std_logic_vector(8 DOWNTO 0);
SIGNAL \U2|WideNor0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \U2|WideNor0_rtl_0|auto_generated|ram_block1a0_PORTADATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
SIGNAL \RESET~clkctrl_I_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \CLK~clkctrl_I_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \U2|Equal0~12474\ : std_logic;
SIGNAL \U2|WideOr3~454\ : std_logic;
SIGNAL \U2|Equal0~12483\ : std_logic;
SIGNAL \U2|WideOr3~455\ : std_logic;
SIGNAL \U2|Equal0~12501\ : std_logic;
SIGNAL \U2|Equal0~12504\ : std_logic;
SIGNAL \U2|Equal0~12505\ : std_logic;
SIGNAL \U2|WideOr7~1377\ : std_logic;
SIGNAL \U2|Equal0~12509\ : std_logic;
SIGNAL \U2|Equal0~12511\ : std_logic;
SIGNAL \U2|WideOr5~917\ : std_logic;
SIGNAL \U2|Equal0~12514\ : std_logic;
SIGNAL \U2|Equal0~12517\ : std_logic;
SIGNAL \U2|WideOr5~918\ : std_logic;
SIGNAL \U2|WideOr5~919\ : std_logic;
SIGNAL \U2|WideOr5~920\ : std_logic;
SIGNAL \U2|WideOr5~921\ : std_logic;
SIGNAL \U2|WideOr5~922\ : std_logic;
SIGNAL \U2|WideOr7~1381\ : std_logic;
SIGNAL \U2|Equal0~12534\ : std_logic;
SIGNAL \U2|WideOr7~1382\ : std_logic;
SIGNAL \U2|Equal0~12539\ : std_logic;
SIGNAL \U2|Equal0~12549\ : std_logic;
SIGNAL \U2|Equal0~12554\ : std_logic;
SIGNAL \U2|WideOr4~660\ : std_logic;
SIGNAL \U2|Equal0~12557\ : std_logic;
SIGNAL \U2|Equal0~12558\ : std_logic;
SIGNAL \U2|WideOr4~661\ : std_logic;
SIGNAL \U2|Equal0~12566\ : std_logic;
SIGNAL \U2|WideOr5~927\ : std_logic;
SIGNAL \U2|WideOr5~928\ : std_logic;
SIGNAL \U2|Equal0~12571\ : std_logic;
SIGNAL \U2|WideOr7~1389\ : std_logic;
SIGNAL \U2|Equal0~12572\ : std_logic;
SIGNAL \U2|Equal0~12574\ : std_logic;
SIGNAL \U2|WideOr7~1390\ : std_logic;
SIGNAL \U2|WideOr7~1391\ : std_logic;
SIGNAL \U2|Equal0~12578\ : std_logic;
SIGNAL \U2|WideOr7~1392\ : std_logic;
SIGNAL \U2|WideOr7~1393\ : std_logic;
SIGNAL \U2|Equal0~12581\ : std_logic;
SIGNAL \U2|Equal0~12583\ : std_logic;
SIGNAL \U2|WideOr7~1394\ : std_logic;
SIGNAL \U2|WideOr7~1395\ : std_logic;
SIGNAL \U2|Equal0~12584\ : std_logic;
SIGNAL \U2|WideOr7~1396\ : std_logic;
SIGNAL \U2|WideOr7~1397\ : std_logic;
SIGNAL \U2|Equal0~12590\ : std_logic;
SIGNAL \U2|WideOr7~1403\ : std_logic;
SIGNAL \U2|WideOr7~1411\ : std_logic;
SIGNAL \U2|WideOr6~903\ : std_logic;
SIGNAL \U2|Equal0~12605\ : std_logic;
SIGNAL \U2|WideOr6~910\ : std_logic;
SIGNAL \U2|WideOr6~919\ : std_logic;
SIGNAL \U2|Equal0~12612\ : std_logic;
SIGNAL \U2|WideOr6~924\ : std_logic;
SIGNAL \U2|Equal0~12615\ : std_logic;
SIGNAL \U2|WideOr6~925\ : std_logic;
SIGNAL \U2|Equal0~12616\ : std_logic;
SIGNAL \U2|Equal0~12617\ : std_logic;
SIGNAL \U2|WideOr6~926\ : std_logic;
SIGNAL \U2|Equal0~12618\ : std_logic;
SIGNAL \U2|WideOr6~927\ : std_logic;
SIGNAL \U2|Equal0~12620\ : std_logic;
SIGNAL \U2|Equal0~12621\ : std_logic;
SIGNAL \U2|Equal0~12624\ : std_logic;
SIGNAL \U2|WideOr5~942\ : std_logic;
SIGNAL \U2|Equal0~12626\ : std_logic;
SIGNAL \U2|WideOr5~943\ : std_logic;
SIGNAL \U2|WideOr5~944\ : std_logic;
SIGNAL \U2|WideOr2~590\ : std_logic;
SIGNAL \U2|WideOr4~669\ : std_logic;
SIGNAL \U2|WideOr4~670\ : std_logic;
SIGNAL \U2|WideOr4~671\ : std_logic;
SIGNAL \U2|WideOr1~907\ : std_logic;
SIGNAL \U2|WideOr0~371\ : std_logic;
SIGNAL \U2|WideOr2~593\ : std_logic;
SIGNAL \U2|WideOr2~595\ : std_logic;
SIGNAL \U2|WideOr1~910\ : std_logic;
SIGNAL \U2|WideOr1~917\ : std_logic;
SIGNAL \U2|WideOr1~918\ : std_logic;
SIGNAL \U2|Equal0~12638\ : std_logic;
SIGNAL \U2|Equal0~12640\ : std_logic;
SIGNAL \U2|Equal0~12645\ : std_logic;
SIGNAL \U2|WideOr7~1414\ : std_logic;
SIGNAL \U2|Equal0~12649\ : std_logic;
SIGNAL \U2|Equal0~12658\ : std_logic;
SIGNAL \U2|Equal0~12660\ : std_logic;
SIGNAL \U2|Equal0~12668\ : std_logic;
SIGNAL \U2|WideOr0~375\ : std_logic;
SIGNAL \U2|WideOr0~326\ : std_logic;
SIGNAL \U2|WideOr0~329\ : std_logic;
SIGNAL \U2|WideOr1~844\ : std_logic;
SIGNAL \U2|WideOr1~847\ : std_logic;
SIGNAL \U2|Equal0~12680\ : std_logic;
SIGNAL \U2|Equal0~12683\ : std_logic;
SIGNAL \U2|Equal0~12684\ : std_logic;
SIGNAL \U2|Equal0~12688\ : std_logic;
SIGNAL \U2|WideOr0~379\ : std_logic;
SIGNAL \U2|WideOr0~380\ : std_logic;
SIGNAL \CLK~combout\ : std_logic;
SIGNAL \CLK~clkctrl\ : std_logic;
SIGNAL \U0|TEMP[0]~347\ : std_logic;
SIGNAL \RESET~combout\ : std_logic;
SIGNAL \RESET~clkctrl\ : std_logic;
SIGNAL \EN~combout\ : std_logic;
SIGNAL \U0|TEMP[0]~348\ : std_logic;
SIGNAL \U0|TEMP[1]~349\ : std_logic;
SIGNAL \U0|TEMP[2]~345\ : std_logic;
SIGNAL \U0|TEMP[1]~346\ : std_logic;
SIGNAL \U2|Equal0~12496\ : std_logic;
SIGNAL \U0|TEMP[2]~350\ : std_logic;
SIGNAL \U0|TEMP[3]~351\ : std_logic;
SIGNAL \U0|TEMP[4]~352\ : std_logic;
SIGNAL \U0|TEMP[5]~342\ : std_logic;
SIGNAL \U0|TEMP[5]~353\ : std_logic;
SIGNAL \U0|TEMP[6]~354\ : std_logic;
SIGNAL \U0|TEMP[7]~340\ : std_logic;
SIGNAL \U0|TEMP[7]~355\ : std_logic;
SIGNAL \U0|TEMP[8]~339\ : std_logic;
SIGNAL \U0|TEMP[8]~356\ : std_logic;
SIGNAL \U0|TEMP[9]~338\ : std_logic;
SIGNAL \U2|Equal0~12525\ : std_logic;
SIGNAL \U0|TEMP[6]~341\ : std_logic;
SIGNAL \U0|TEMP[4]~343\ : std_logic;
SIGNAL \U2|Equal0~12526\ : std_logic;
SIGNAL \U2|Equal0~12527\ : std_logic;
SIGNAL \U0|TEMP[3]~344\ : std_logic;
SIGNAL \U2|Equal0~12488\ : std_logic;
SIGNAL \U2|Equal0~12481\ : std_logic;
SIGNAL \U2|Equal0~12508\ : std_logic;
SIGNAL \U2|Equal0~12585\ : std_logic;
SIGNAL \U2|WideOr3~462\ : std_logic;
SIGNAL \U2|Equal0~12469\ : std_logic;
SIGNAL \U2|Equal0~12468\ : std_logic;
SIGNAL \U2|Equal0~12520\ : std_logic;
SIGNAL \U2|Equal0~12651\ : std_logic;
SIGNAL \U2|Equal0~12497\ : std_logic;
SIGNAL \U2|Equal0~12573\ : std_logic;
SIGNAL \U2|Equal0~12482\ : std_logic;
SIGNAL \U2|Equal0~12533\ : std_logic;
SIGNAL \U2|Equal0~12589\ : std_logic;
SIGNAL \U2|WideOr7~1401\ : std_logic;
SIGNAL \U2|Equal0~12493\ : std_logic;
SIGNAL \U2|Equal0~12500\ : std_logic;
SIGNAL \U2|Equal0~12588\ : std_logic;
SIGNAL \U2|Equal0~12577\ : std_logic;
SIGNAL \U2|Equal0~12510\ : std_logic;
SIGNAL \U2|Equal0~12555\ : std_logic;
SIGNAL \U2|WideOr7~1400\ : std_logic;
SIGNAL \U2|WideOr7~1402\ : std_logic;
SIGNAL \U2|Equal0~12635\ : std_logic;
SIGNAL \U2|Equal0~12592\ : std_logic;
SIGNAL \U2|Equal0~12524\ : std_logic;
SIGNAL \U2|Equal0~12550\ : std_logic;
SIGNAL \U2|Equal0~12653\ : std_logic;
SIGNAL \U2|WideOr7~1404\ : std_logic;
SIGNAL \U2|Equal0~12593\ : std_logic;
SIGNAL \U2|Equal0~12480\ : std_logic;
SIGNAL \U2|Equal0~12580\ : std_logic;
SIGNAL \U2|Equal0~12678\ : std_logic;
SIGNAL \U2|Equal0~12595\ : std_logic;
SIGNAL \U2|WideOr7~1405\ : std_logic;
SIGNAL \U2|WideOr7~1406\ : std_logic;
SIGNAL \U2|Equal0~12485\ : std_logic;
SIGNAL \U2|Equal0~12486\ : std_logic;
SIGNAL \U2|Equal0~12529\ : std_logic;
SIGNAL \U2|Equal0~12530\ : std_logic;
SIGNAL \U2|Equal0~12677\ : std_logic;
SIGNAL \U2|WideOr7~1380\ : std_logic;
SIGNAL \U2|Equal0~12479\ : std_logic;
SIGNAL \U2|Equal0~12537\ : std_logic;
SIGNAL \U2|Equal0~12502\ : std_logic;
SIGNAL \U2|Equal0~12490\ : std_logic;
SIGNAL \U2|Equal0~12639\ : std_logic;
SIGNAL \U2|WideOr7~1384\ : std_logic;
SIGNAL \U2|Equal0~12540\ : std_logic;
SIGNAL \U2|Equal0~12531\ : std_logic;
SIGNAL \U2|Equal0~12541\ : std_logic;
SIGNAL \U2|Equal0~12471\ : std_logic;
SIGNAL \U2|Equal0~12487\ : std_logic;
SIGNAL \U2|Equal0~12633\ : std_logic;
SIGNAL \U2|WideOr7~1383\ : std_logic;
SIGNAL \U2|WideOr7~1385\ : std_logic;
SIGNAL \U2|Equal0~12528\ : std_logic;
SIGNAL \U2|Equal0~12506\ : std_logic;
SIGNAL \U2|Equal0~12634\ : std_logic;
SIGNAL \U2|Equal0~12637\ : std_logic;
SIGNAL \U2|WideOr3~457\ : std_logic;
SIGNAL \U2|Equal0~12679\ : std_logic;
SIGNAL \U2|Equal0~12494\ : std_logic;
SIGNAL \U2|Equal0~12495\ : std_logic;
SIGNAL \U2|WideOr3~456\ : std_logic;
SIGNAL \U2|WideOr3~458\ : std_logic;
SIGNAL \U2|WideOr7~1386\ : std_logic;
SIGNAL \U2|Equal0~12559\ : std_logic;
SIGNAL \U2|Equal0~12641\ : std_logic;
SIGNAL \U2|Equal0~12560\ : std_logic;
SIGNAL \U2|WideOr4~662\ : std_logic;
SIGNAL \U2|Equal0~12553\ : std_logic;
SIGNAL \U2|Equal0~12513\ : std_logic;
SIGNAL \U2|Equal0~12476\ : std_logic;
SIGNAL \U2|Equal0~12552\ : std_logic;
SIGNAL \U2|Equal0~12551\ : std_logic;
SIGNAL \U2|WideOr1~904\ : std_logic;
SIGNAL \U2|WideOr4~659\ : std_logic;
SIGNAL \U2|Equal0~12547\ : std_logic;
SIGNAL \U2|Equal0~12518\ : std_logic;
SIGNAL \U2|Equal0~12546\ : std_logic;
SIGNAL \U2|Equal0~12512\ : std_logic;
SIGNAL \U2|Equal0~12543\ : std_logic;
SIGNAL \U2|Equal0~12515\ : std_logic;
SIGNAL \U2|Equal0~12532\ : std_logic;
SIGNAL \U2|Equal0~12472\ : std_logic;
SIGNAL \U2|Equal0~12544\ : std_logic;
SIGNAL \U2|Equal0~12545\ : std_logic;
SIGNAL \U2|Equal0~12542\ : std_logic;
SIGNAL \U2|WideOr4~657\ : std_logic;
SIGNAL \U2|WideOr4~658\ : std_logic;
SIGNAL \U2|WideOr4~663\ : std_logic;
SIGNAL \U2|Equal0~12521\ : std_logic;
SIGNAL \U2|Equal0~12523\ : std_logic;
SIGNAL \U2|Equal0~12569\ : std_logic;
SIGNAL \U2|WideOr3~459\ : std_logic;
SIGNAL \U2|Equal0~12682\ : std_logic;
SIGNAL \U2|Equal0~12522\ : std_logic;
SIGNAL \U2|WideOr2~588\ : std_logic;
SIGNAL \U2|WideOr7~1387\ : std_logic;
SIGNAL \U2|Equal0~12568\ : std_logic;
SIGNAL \U2|Equal0~12503\ : std_logic;
SIGNAL \U2|Equal0~12564\ : std_logic;
SIGNAL \U2|WideOr5~925\ : std_logic;
SIGNAL \U2|Equal0~12565\ : std_logic;
SIGNAL \U2|WideOr5~926\ : std_logic;
SIGNAL \U2|Equal0~12473\ : std_logic;
SIGNAL \U2|Equal0~12562\ : std_logic;
SIGNAL \U2|Equal0~12681\ : std_logic;
SIGNAL \U2|WideOr5~923\ : std_logic;
SIGNAL \U2|WideOr5~924\ : std_logic;
SIGNAL \U2|WideOr5~929\ : std_logic;
SIGNAL \U2|WideOr7~1388\ : std_logic;
SIGNAL \U2|WideOr7~1398\ : std_logic;
SIGNAL \U2|Equal0~12636\ : std_logic;
SIGNAL \U2|WideOr2~585\ : std_logic;
SIGNAL \U2|WideOr2~586\ : std_logic;
SIGNAL \U2|Equal0~12470\ : std_logic;
SIGNAL \U2|Equal0~12489\ : std_logic;
SIGNAL \U2|WideOr1~903\ : std_logic;
SIGNAL \U2|WideOr7~1371\ : std_logic;
SIGNAL \U2|WideOr3~453\ : std_logic;
SIGNAL \U2|Equal0~12491\ : std_logic;
SIGNAL \U2|Equal0~12492\ : std_logic;
SIGNAL \U2|WideOr7~1372\ : std_logic;
SIGNAL \U2|Equal0~12498\ : std_logic;
SIGNAL \U2|Equal0~12499\ : std_logic;
SIGNAL \U2|WideOr7~1373\ : std_logic;
SIGNAL \U2|WideOr6~899\ : std_logic;
SIGNAL \U2|WideOr7~1374\ : std_logic;
SIGNAL \U2|WideOr7~1375\ : std_logic;
SIGNAL \U2|WideOr7~1376\ : std_logic;
SIGNAL \U2|WideOr7~1378\ : std_logic;
SIGNAL \U2|WideOr7~1379\ : std_logic;
SIGNAL \U2|WideOr7~1413\ : std_logic;
SIGNAL \U3|Q[0]~feeder\ : std_logic;
SIGNAL \U2|Equal0~12664\ : std_logic;
SIGNAL \U2|Equal0~12665\ : std_logic;
SIGNAL \U2|Equal0~12477\ : std_logic;
SIGNAL \U2|Equal0~12662\ : std_logic;
SIGNAL \U2|Equal0~12661\ : std_logic;
SIGNAL \U2|WideOr6~920\ : std_logic;
SIGNAL \U2|Equal0~12567\ : std_logic;
SIGNAL \U2|Equal0~12643\ : std_logic;
SIGNAL \U2|Equal0~12659\ : std_logic;
SIGNAL \U2|WideOr2~589\ : std_logic;
SIGNAL \U2|WideOr6~918\ : std_logic;
SIGNAL \U2|WideOr6~916\ : std_logic;
SIGNAL \U2|Equal0~12548\ : std_logic;
SIGNAL \U2|Equal0~12579\ : std_logic;
SIGNAL \U2|WideOr6~914\ : std_logic;
SIGNAL \U2|WideOr6~915\ : std_logic;
SIGNAL \U2|WideOr6~917\ : std_logic;
SIGNAL \U2|WideOr6~921\ : std_logic;
SIGNAL \U2|Equal0~12600\ : std_logic;
SIGNAL \U2|Equal0~12601\ : std_logic;
SIGNAL \U2|Equal0~12657\ : std_logic;
SIGNAL \U2|Equal0~12516\ : std_logic;
SIGNAL \U2|Equal0~12602\ : std_logic;
SIGNAL \U2|WideOr6~900\ : std_logic;
SIGNAL \U2|Equal0~12582\ : std_logic;
SIGNAL \U2|Equal0~12598\ : std_logic;
SIGNAL \U2|WideOr6~904\ : std_logic;
SIGNAL \U2|Equal0~12519\ : std_logic;
SIGNAL \U2|WideOr6~902\ : std_logic;
SIGNAL \U2|Equal0~12603\ : std_logic;
SIGNAL \U2|Equal0~12536\ : std_logic;
SIGNAL \U2|WideOr6~901\ : std_logic;
SIGNAL \U2|WideOr6~905\ : std_logic;
SIGNAL \U2|WideOr3~464\ : std_logic;
SIGNAL \U2|WideOr6~906\ : std_logic;
SIGNAL \U2|Equal0~12685\ : std_logic;
SIGNAL \U2|Equal0~12686\ : std_logic;
SIGNAL \U2|WideOr6~909\ : std_logic;
SIGNAL \U2|Equal0~12475\ : std_logic;
SIGNAL \U2|Equal0~12607\ : std_logic;
SIGNAL \U2|WideOr6~911\ : std_logic;
SIGNAL \U2|Equal0~12606\ : std_logic;
SIGNAL \U2|Equal0~12596\ : std_logic;
SIGNAL \U2|WideOr6~907\ : std_logic;
SIGNAL \U2|WideOr6~908\ : std_logic;
SIGNAL \U2|WideOr6~912\ : std_logic;
SIGNAL \U2|WideOr6~913\ : std_logic;
SIGNAL \U2|WideOr6~930\ : std_logic;
SIGNAL \U3|Q[1]~feeder\ : std_logic;
SIGNAL \U2|Equal0~12670\ : std_logic;
SIGNAL \U2|Equal0~12591\ : std_logic;
SIGNAL \U2|WideOr5~930\ : std_logic;
SIGNAL \U2|WideOr5~931\ : std_logic;
SIGNAL \U2|WideOr6~898\ : std_logic;
SIGNAL \U2|WideOr5~932\ : std_logic;
SIGNAL \U2|WideOr5~933\ : std_logic;
SIGNAL \U2|WideOr5~934\ : std_logic;
SIGNAL \U2|WideOr3~467\ : std_logic;
SIGNAL \U2|WideOr5~935\ : std_logic;
SIGNAL \U2|Equal0~12619\ : std_logic;
SIGNAL \U2|Equal0~12597\ : std_logic;
SIGNAL \U2|Equal0~12687\ : std_logic;
SIGNAL \U2|Equal0~12666\ : std_logic;
SIGNAL \U2|Equal0~12671\ : std_logic;
SIGNAL \U2|WideOr5~936\ : std_logic;
SIGNAL \U2|WideOr5~937\ : std_logic;
SIGNAL \U2|Equal0~12614\ : std_logic;
SIGNAL \U2|WideOr6~928\ : std_logic;
SIGNAL \U2|WideOr6~889\ : std_logic;
SIGNAL \U2|WideOr6~885\ : std_logic;
SIGNAL \U2|WideOr6~931\ : std_logic;
SIGNAL \U2|WideOr6~923\ : std_logic;
SIGNAL \U2|Equal0~12667\ : std_logic;
SIGNAL \U2|Equal0~12561\ : std_logic;
SIGNAL \U2|Equal0~12611\ : std_logic;
SIGNAL \U2|WideOr6~922\ : std_logic;
SIGNAL \U2|WideOr6~929\ : std_logic;
SIGNAL \U2|WideOr5~938\ : std_logic;
SIGNAL \U2|Equal0~12673\ : std_logic;
SIGNAL \U2|Equal0~12672\ : std_logic;
SIGNAL \U2|WideOr3~470\ : std_logic;
SIGNAL \U2|WideOr3~469\ : std_logic;
SIGNAL \U2|WideOr3~471\ : std_logic;
SIGNAL \U2|Equal0~12576\ : std_logic;
SIGNAL \U2|WideOr3~468\ : std_logic;
SIGNAL \U2|WideOr3~472\ : std_logic;
SIGNAL \U2|Equal0~12623\ : std_logic;
SIGNAL \U2|Equal0~12674\ : std_logic;
SIGNAL \U2|Equal0~12625\ : std_logic;
SIGNAL \U2|WideOr5~941\ : std_logic;
SIGNAL \U2|Equal0~12622\ : std_logic;
SIGNAL \U2|Equal0~12689\ : std_logic;
SIGNAL \U2|WideOr5~939\ : std_logic;
SIGNAL \U2|WideOr5~940\ : std_logic;
SIGNAL \U2|WideOr5~945\ : std_logic;
SIGNAL \U2|WideOr5~946\ : std_logic;
SIGNAL \U2|WideOr5~947\ : std_logic;
SIGNAL \U3|Q[2]~feeder\ : std_logic;
SIGNAL \U2|Equal0~12655\ : std_logic;
SIGNAL \U2|Equal0~12632\ : std_logic;
SIGNAL \U2|WideOr7~1409\ : std_logic;
SIGNAL \U2|Equal0~12656\ : std_logic;
SIGNAL \U2|WideOr7~1410\ : std_logic;
SIGNAL \U2|WideOr3~463\ : std_logic;
SIGNAL \U2|Equal0~12654\ : std_logic;