Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Dec 05 22:04:25 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dds -c dds
Info: Selected device EP2C5Q208C8 for design "dds"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 529 of 529 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5Q208I8 is compatible
    Info: Device EP2C8Q208C8 is compatible
    Info: Device EP2C8Q208I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS41p/nCEO~ is reserved at location 108
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: No exact pin location assignment(s) for 22 pins of 22 total pins
    Info: Pin Q[0] not assigned to an exact location on the device
    Info: Pin Q[1] not assigned to an exact location on the device
    Info: Pin Q[2] not assigned to an exact location on the device
    Info: Pin Q[3] not assigned to an exact location on the device
    Info: Pin Q[4] not assigned to an exact location on the device
    Info: Pin Q[5] not assigned to an exact location on the device
    Info: Pin Q[6] not assigned to an exact location on the device
    Info: Pin Q[7] not assigned to an exact location on the device
    Info: Pin Q[8] not assigned to an exact location on the device
    Info: Pin CLK not assigned to an exact location on the device
    Info: Pin K[8] not assigned to an exact location on the device
    Info: Pin K[7] not assigned to an exact location on the device
    Info: Pin K[6] not assigned to an exact location on the device
    Info: Pin K[5] not assigned to an exact location on the device
    Info: Pin K[4] not assigned to an exact location on the device
    Info: Pin K[3] not assigned to an exact location on the device
    Info: Pin K[2] not assigned to an exact location on the device
    Info: Pin K[1] not assigned to an exact location on the device
    Info: Pin K[0] not assigned to an exact location on the device
    Info: Pin RESET not assigned to an exact location on the device
    Info: Pin EN not assigned to an exact location on the device
    Info: Pin K[9] not assigned to an exact location on the device
Info: Automatically promoted node CLK (placed in PIN 23 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Automatically promoted node RESET (placed in PIN 24 (CLK1, LVDSCLK0n, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 20 (unused VREF, 3.30 VCCIO, 11 input, 9 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  30 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  35 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  36 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  36 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 9.930 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y7; Fanout = 41; REG Node = 'REG1:U1|Q[8]'
    Info: 2: + IC(1.335 ns) + CELL(0.529 ns) = 1.864 ns; Loc. = LAB_X17_Y8; Fanout = 16; COMB Node = 'ROM:U2|Equal0~12487'
    Info: 3: + IC(1.521 ns) + CELL(0.370 ns) = 3.755 ns; Loc. = LAB_X20_Y7; Fanout = 3; COMB Node = 'ROM:U2|Equal0~12641'
    Info: 4: + IC(0.187 ns) + CELL(0.616 ns) = 4.558 ns; Loc. = LAB_X20_Y7; Fanout = 1; COMB Node = 'ROM:U2|WideOr6~904'
    Info: 5: + IC(1.320 ns) + CELL(0.206 ns) = 6.084 ns; Loc. = LAB_X20_Y8; Fanout = 1; COMB Node = 'ROM:U2|WideOr6~905'
    Info: 6: + IC(1.165 ns) + CELL(0.370 ns) = 7.619 ns; Loc. = LAB_X21_Y10; Fanout = 2; COMB Node = 'ROM:U2|WideOr6~906'
    Info: 7: + IC(0.605 ns) + CELL(0.206 ns) = 8.430 ns; Loc. = LAB_X21_Y10; Fanout = 1; COMB Node = 'ROM:U2|WideOr4~672'
    Info: 8: + IC(0.893 ns) + CELL(0.499 ns) = 9.822 ns; Loc. = LAB_X21_Y7; Fanout = 1; COMB Node = 'ROM:U2|WideOr4~673'
    Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 9.930 ns; Loc. = LAB_X21_Y7; Fanout = 1; REG Node = 'ROM:U2|OUTP[3]'
    Info: Total cell delay = 2.904 ns ( 29.24 % )
    Info: Total interconnect delay = 7.026 ns ( 70.76 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 6%
    Info: The peak interconnect region extends from location X14_Y0 to location X28_Y14
Info: Fitter routing operations ending: elapsed time is 00:00:03
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 9 output pins without output pin load capacitance assignment
    Info: Pin "Q[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "Q[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin Q[8] has GND driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 4 warnings
    Info: Allocated 172 megabytes of memory during processing
    Info: Processing ended: Fri Dec 05 22:04:39 2008
    Info: Elapsed time: 00:00:14