{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register REG1:U1\|Q\[5\] register ROM:U2\|OUTP\[2\] 86.95 MHz 11.501 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 86.95 MHz between source register \"REG1:U1\|Q\[5\]\" and destination register \"ROM:U2\|OUTP\[2\]\" (period= 11.501 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.228 ns + Longest register register " "Info: + Longest register to register delay is 11.228 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG1:U1\|Q\[5\] 1 REG LCFF_X18_Y8_N23 57 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y8_N23; Fanout = 57; REG Node = 'REG1:U1\|Q\[5\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG1:U1|Q[5] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.463 ns) + CELL(0.202 ns) 0.665 ns ROM:U2\|Equal0~12469 2 COMB LCCOMB_X18_Y8_N16 7 " "Info: 2: + IC(0.463 ns) + CELL(0.202 ns) = 0.665 ns; Loc. = LCCOMB_X18_Y8_N16; Fanout = 7; COMB Node = 'ROM:U2\|Equal0~12469'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.665 ns" { REG1:U1|Q[5] ROM:U2|Equal0~12469 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.278 ns) + CELL(0.370 ns) 3.313 ns ROM:U2\|Equal0~12614 3 COMB LCCOMB_X18_Y7_N18 2 " "Info: 3: + IC(2.278 ns) + CELL(0.370 ns) = 3.313 ns; Loc. = LCCOMB_X18_Y7_N18; Fanout = 2; COMB Node = 'ROM:U2\|Equal0~12614'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.648 ns" { ROM:U2|Equal0~12469 ROM:U2|Equal0~12614 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.376 ns) + CELL(0.370 ns) 6.059 ns ROM:U2\|WideOr6~925 4 COMB LCCOMB_X18_Y7_N28 1 " "Info: 4: + IC(2.376 ns) + CELL(0.370 ns) = 6.059 ns; Loc. = LCCOMB_X18_Y7_N28; Fanout = 1; COMB Node = 'ROM:U2\|WideOr6~925'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.746 ns" { ROM:U2|Equal0~12614 ROM:U2|WideOr6~925 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.623 ns) 7.053 ns ROM:U2\|WideOr6~926 5 COMB LCCOMB_X18_Y7_N16 1 " "Info: 5: + IC(0.371 ns) + CELL(0.623 ns) = 7.053 ns; Loc. = LCCOMB_X18_Y7_N16; Fanout = 1; COMB Node = 'ROM:U2\|WideOr6~926'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { ROM:U2|WideOr6~925 ROM:U2|WideOr6~926 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.370 ns) 7.806 ns ROM:U2\|WideOr6~927 6 COMB LCCOMB_X18_Y7_N6 1 " "Info: 6: + IC(0.383 ns) + CELL(0.370 ns) = 7.806 ns; Loc. = LCCOMB_X18_Y7_N6; Fanout = 1; COMB Node = 'ROM:U2\|WideOr6~927'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.753 ns" { ROM:U2|WideOr6~926 ROM:U2|WideOr6~927 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.614 ns) 8.814 ns ROM:U2\|WideOr6~929 7 COMB LCCOMB_X18_Y7_N0 2 " "Info: 7: + IC(0.394 ns) + CELL(0.614 ns) = 8.814 ns; Loc. = LCCOMB_X18_Y7_N0; Fanout = 2; COMB Node = 'ROM:U2\|WideOr6~929'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.008 ns" { ROM:U2|WideOr6~927 ROM:U2|WideOr6~929 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.355 ns) + CELL(0.206 ns) 10.375 ns ROM:U2\|WideOr5~938 8 COMB LCCOMB_X21_Y7_N24 1 " "Info: 8: + IC(1.355 ns) + CELL(0.206 ns) = 10.375 ns; Loc. = LCCOMB_X21_Y7_N24; Fanout = 1; COMB Node = 'ROM:U2\|WideOr5~938'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { ROM:U2|WideOr6~929 ROM:U2|WideOr5~938 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.370 ns) 11.120 ns ROM:U2\|WideOr5~947 9 COMB LCCOMB_X21_Y7_N30 1 " "Info: 9: + IC(0.375 ns) + CELL(0.370 ns) = 11.120 ns; Loc. = LCCOMB_X21_Y7_N30; Fanout = 1; COMB Node = 'ROM:U2\|WideOr5~947'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.745 ns" { ROM:U2|WideOr5~938 ROM:U2|WideOr5~947 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 11.228 ns ROM:U2\|OUTP\[2\] 10 REG LCFF_X21_Y7_N31 1 " "Info: 10: + IC(0.000 ns) + CELL(0.108 ns) = 11.228 ns; Loc. = LCFF_X21_Y7_N31; Fanout = 1; REG Node = 'ROM:U2\|OUTP\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { ROM:U2|WideOr5~947 ROM:U2|OUTP[2] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.233 ns ( 28.79 % ) " "Info: Total cell delay = 3.233 ns ( 28.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.995 ns ( 71.21 % ) " "Info: Total interconnect delay = 7.995 ns ( 71.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.228 ns" { REG1:U1|Q[5] ROM:U2|Equal0~12469 ROM:U2|Equal0~12614 ROM:U2|WideOr6~925 ROM:U2|WideOr6~926 ROM:U2|WideOr6~927 ROM:U2|WideOr6~929 ROM:U2|WideOr5~938 ROM:U2|WideOr5~947 ROM:U2|OUTP[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.228 ns" { REG1:U1|Q[5] ROM:U2|Equal0~12469 ROM:U2|Equal0~12614 ROM:U2|WideOr6~925 ROM:U2|WideOr6~926 ROM:U2|WideOr6~927 ROM:U2|WideOr6~929 ROM:U2|WideOr5~938 ROM:U2|WideOr5~947 ROM:U2|OUTP[2] } { 0.000ns 0.463ns 2.278ns 2.376ns 0.371ns 0.383ns 0.394ns 1.355ns 0.375ns 0.000ns } { 0.000ns 0.202ns 0.370ns 0.370ns 0.623ns 0.370ns 0.614ns 0.206ns 0.370ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.009 ns - Smallest " "Info: - Smallest clock skew is -0.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.774 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 46 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 46; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.825 ns) + CELL(0.666 ns) 2.774 ns ROM:U2\|OUTP\[2\] 3 REG LCFF_X21_Y7_N31 1 " "Info: 3: + IC(0.825 ns) + CELL(0.666 ns) = 2.774 ns; Loc. = LCFF_X21_Y7_N31; Fanout = 1; REG Node = 'ROM:U2\|OUTP\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { CLK~clkctrl ROM:U2|OUTP[2] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.10 % ) " "Info: Total cell delay = 1.806 ns ( 65.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.968 ns ( 34.90 % ) " "Info: Total interconnect delay = 0.968 ns ( 34.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { CLK CLK~clkctrl ROM:U2|OUTP[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { CLK CLK~combout CLK~clkctrl ROM:U2|OUTP[2] } { 0.000ns 0.000ns 0.143ns 0.825ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.783 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.783 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 46 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 46; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.834 ns) + CELL(0.666 ns) 2.783 ns REG1:U1\|Q\[5\] 3 REG LCFF_X18_Y8_N23 57 " "Info: 3: + IC(0.834 ns) + CELL(0.666 ns) = 2.783 ns; Loc. = LCFF_X18_Y8_N23; Fanout = 57; REG Node = 'REG1:U1\|Q\[5\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK~clkctrl REG1:U1|Q[5] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.89 % ) " "Info: Total cell delay = 1.806 ns ( 64.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.977 ns ( 35.11 % ) " "Info: Total interconnect delay = 0.977 ns ( 35.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.783 ns" { CLK CLK~clkctrl REG1:U1|Q[5] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.783 ns" { CLK CLK~combout CLK~clkctrl REG1:U1|Q[5] } { 0.000ns 0.000ns 0.143ns 0.834ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { CLK CLK~clkctrl ROM:U2|OUTP[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { CLK CLK~combout CLK~clkctrl ROM:U2|OUTP[2] } { 0.000ns 0.000ns 0.143ns 0.825ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.783 ns" { CLK CLK~clkctrl REG1:U1|Q[5] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.783 ns" { CLK CLK~combout CLK~clkctrl REG1:U1|Q[5] } { 0.000ns 0.000ns 0.143ns 0.834ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 129 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.228 ns" { REG1:U1|Q[5] ROM:U2|Equal0~12469 ROM:U2|Equal0~12614 ROM:U2|WideOr6~925 ROM:U2|WideOr6~926 ROM:U2|WideOr6~927 ROM:U2|WideOr6~929 ROM:U2|WideOr5~938 ROM:U2|WideOr5~947 ROM:U2|OUTP[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "11.228 ns" { REG1:U1|Q[5] ROM:U2|Equal0~12469 ROM:U2|Equal0~12614 ROM:U2|WideOr6~925 ROM:U2|WideOr6~926 ROM:U2|WideOr6~927 ROM:U2|WideOr6~929 ROM:U2|WideOr5~938 ROM:U2|WideOr5~947 ROM:U2|OUTP[2] } { 0.000ns 0.463ns 2.278ns 2.376ns 0.371ns 0.383ns 0.394ns 1.355ns 0.375ns 0.000ns } { 0.000ns 0.202ns 0.370ns 0.370ns 0.623ns 0.370ns 0.614ns 0.206ns 0.370ns 0.108ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.774 ns" { CLK CLK~clkctrl ROM:U2|OUTP[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.774 ns" { CLK CLK~combout CLK~clkctrl ROM:U2|OUTP[2] } { 0.000ns 0.000ns 0.143ns 0.825ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.783 ns" { CLK CLK~clkctrl REG1:U1|Q[5] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.783 ns" { CLK CLK~combout CLK~clkctrl REG1:U1|Q[5] } { 0.000ns 0.000ns 0.143ns 0.834ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "SUM99:U0\|TEMP\[9\] K\[6\] CLK 6.293 ns register " "Info: tsu for register \"SUM99:U0\|TEMP\[9\]\" (data pin = \"K\[6\]\", clock pin = \"CLK\") is 6.293 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.120 ns + Longest pin register " "Info: + Longest pin to register delay is 9.120 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 0.975 ns K\[6\] 1 PIN PIN_141 2 " "Info: 1: + IC(0.000 ns) + CELL(0.975 ns) = 0.975 ns; Loc. = PIN_141; Fanout = 2; PIN Node = 'K\[6\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { K[6] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.763 ns) + CELL(0.596 ns) 8.334 ns SUM99:U0\|TEMP\[6\]~354 2 COMB LCCOMB_X20_Y4_N16 2 " "Info: 2: + IC(6.763 ns) + CELL(0.596 ns) = 8.334 ns; Loc. = LCCOMB_X20_Y4_N16; Fanout = 2; COMB Node = 'SUM99:U0\|TEMP\[6\]~354'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.359 ns" { K[6] SUM99:U0|TEMP[6]~354 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.420 ns SUM99:U0\|TEMP\[7\]~355 3 COMB LCCOMB_X20_Y4_N18 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 8.420 ns; Loc. = LCCOMB_X20_Y4_N18; Fanout = 2; COMB Node = 'SUM99:U0\|TEMP\[7\]~355'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { SUM99:U0|TEMP[6]~354 SUM99:U0|TEMP[7]~355 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.506 ns SUM99:U0\|TEMP\[8\]~356 4 COMB LCCOMB_X20_Y4_N20 1 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 8.506 ns; Loc. = LCCOMB_X20_Y4_N20; Fanout = 1; COMB Node = 'SUM99:U0\|TEMP\[8\]~356'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { SUM99:U0|TEMP[7]~355 SUM99:U0|TEMP[8]~356 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 9.012 ns SUM99:U0\|TEMP\[9\]~338 5 COMB LCCOMB_X20_Y4_N22 1 " "Info: 5: + IC(0.000 ns) + CELL(0.506 ns) = 9.012 ns; Loc. = LCCOMB_X20_Y4_N22; Fanout = 1; COMB Node = 'SUM99:U0\|TEMP\[9\]~338'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { SUM99:U0|TEMP[8]~356 SUM99:U0|TEMP[9]~338 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.120 ns SUM99:U0\|TEMP\[9\] 6 REG LCFF_X20_Y4_N23 3 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 9.120 ns; Loc. = LCFF_X20_Y4_N23; Fanout = 3; REG Node = 'SUM99:U0\|TEMP\[9\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { SUM99:U0|TEMP[9]~338 SUM99:U0|TEMP[9] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.357 ns ( 25.84 % ) " "Info: Total cell delay = 2.357 ns ( 25.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.763 ns ( 74.16 % ) " "Info: Total interconnect delay = 6.763 ns ( 74.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.120 ns" { K[6] SUM99:U0|TEMP[6]~354 SUM99:U0|TEMP[7]~355 SUM99:U0|TEMP[8]~356 SUM99:U0|TEMP[9]~338 SUM99:U0|TEMP[9] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.120 ns" { K[6] K[6]~combout SUM99:U0|TEMP[6]~354 SUM99:U0|TEMP[7]~355 SUM99:U0|TEMP[8]~356 SUM99:U0|TEMP[9]~338 SUM99:U0|TEMP[9] } { 0.000ns 0.000ns 6.763ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.975ns 0.596ns 0.086ns 0.086ns 0.506ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.787 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 46 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 46; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.666 ns) 2.787 ns SUM99:U0\|TEMP\[9\] 3 REG LCFF_X20_Y4_N23 3 " "Info: 3: + IC(0.838 ns) + CELL(0.666 ns) = 2.787 ns; Loc. = LCFF_X20_Y4_N23; Fanout = 3; REG Node = 'SUM99:U0\|TEMP\[9\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { CLK~clkctrl SUM99:U0|TEMP[9] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.80 % ) " "Info: Total cell delay = 1.806 ns ( 64.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns ( 35.20 % ) " "Info: Total interconnect delay = 0.981 ns ( 35.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { CLK CLK~clkctrl SUM99:U0|TEMP[9] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { CLK CLK~combout CLK~clkctrl SUM99:U0|TEMP[9] } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.120 ns" { K[6] SUM99:U0|TEMP[6]~354 SUM99:U0|TEMP[7]~355 SUM99:U0|TEMP[8]~356 SUM99:U0|TEMP[9]~338 SUM99:U0|TEMP[9] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.120 ns" { K[6] K[6]~combout SUM99:U0|TEMP[6]~354 SUM99:U0|TEMP[7]~355 SUM99:U0|TEMP[8]~356 SUM99:U0|TEMP[9]~338 SUM99:U0|TEMP[9] } { 0.000ns 0.000ns 6.763ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.975ns 0.596ns 0.086ns 0.086ns 0.506ns 0.108ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { CLK CLK~clkctrl SUM99:U0|TEMP[9] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { CLK CLK~combout CLK~clkctrl SUM99:U0|TEMP[9] } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[7\] REG2:U3\|Q\[7\] 9.279 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[7\]\" through register \"REG2:U3\|Q\[7\]\" is 9.279 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.782 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 46 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 46; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.666 ns) 2.782 ns REG2:U3\|Q\[7\] 3 REG LCFF_X17_Y8_N19 1 " "Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X17_Y8_N19; Fanout = 1; REG Node = 'REG2:U3\|Q\[7\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { CLK~clkctrl REG2:U3|Q[7] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 107 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.92 % ) " "Info: Total cell delay = 1.806 ns ( 64.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.976 ns ( 35.08 % ) " "Info: Total interconnect delay = 0.976 ns ( 35.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK CLK~clkctrl REG2:U3|Q[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~combout CLK~clkctrl REG2:U3|Q[7] } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 107 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.193 ns + Longest register pin " "Info: + Longest register to pin delay is 6.193 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG2:U3\|Q\[7\] 1 REG LCFF_X17_Y8_N19 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y8_N19; Fanout = 1; REG Node = 'REG2:U3\|Q\[7\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { REG2:U3|Q[7] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 107 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.097 ns) + CELL(3.096 ns) 6.193 ns Q\[7\] 2 PIN PIN_32 0 " "Info: 2: + IC(3.097 ns) + CELL(3.096 ns) = 6.193 ns; Loc. = PIN_32; Fanout = 0; PIN Node = 'Q\[7\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.193 ns" { REG2:U3|Q[7] Q[7] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 49.99 % ) " "Info: Total cell delay = 3.096 ns ( 49.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.097 ns ( 50.01 % ) " "Info: Total interconnect delay = 3.097 ns ( 50.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.193 ns" { REG2:U3|Q[7] Q[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.193 ns" { REG2:U3|Q[7] Q[7] } { 0.000ns 3.097ns } { 0.000ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { CLK CLK~clkctrl REG2:U3|Q[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { CLK CLK~combout CLK~clkctrl REG2:U3|Q[7] } { 0.000ns 0.000ns 0.143ns 0.833ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.193 ns" { REG2:U3|Q[7] Q[7] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.193 ns" { REG2:U3|Q[7] Q[7] } { 0.000ns 3.097ns } { 0.000ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "SUM99:U0\|TEMP\[4\] K\[4\] CLK -0.364 ns register " "Info: th for register \"SUM99:U0\|TEMP\[4\]\" (data pin = \"K\[4\]\", clock pin = \"CLK\") is -0.364 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.787 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 46 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 46; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.666 ns) 2.787 ns SUM99:U0\|TEMP\[4\] 3 REG LCFF_X20_Y4_N13 4 " "Info: 3: + IC(0.838 ns) + CELL(0.666 ns) = 2.787 ns; Loc. = LCFF_X20_Y4_N13; Fanout = 4; REG Node = 'SUM99:U0\|TEMP\[4\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { CLK~clkctrl SUM99:U0|TEMP[4] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.80 % ) " "Info: Total cell delay = 1.806 ns ( 64.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns ( 35.20 % ) " "Info: Total interconnect delay = 0.981 ns ( 35.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { CLK CLK~clkctrl SUM99:U0|TEMP[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { CLK CLK~combout CLK~clkctrl SUM99:U0|TEMP[4] } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.457 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.457 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns K\[4\] 1 PIN PIN_27 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_27; Fanout = 2; PIN Node = 'K\[4\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { K[4] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.585 ns) + CELL(0.624 ns) 3.349 ns SUM99:U0\|TEMP\[4\]~343 2 COMB LCCOMB_X20_Y4_N12 1 " "Info: 2: + IC(1.585 ns) + CELL(0.624 ns) = 3.349 ns; Loc. = LCCOMB_X20_Y4_N12; Fanout = 1; COMB Node = 'SUM99:U0\|TEMP\[4\]~343'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.209 ns" { K[4] SUM99:U0|TEMP[4]~343 } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.457 ns SUM99:U0\|TEMP\[4\] 3 REG LCFF_X20_Y4_N13 4 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.457 ns; Loc. = LCFF_X20_Y4_N13; Fanout = 4; REG Node = 'SUM99:U0\|TEMP\[4\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { SUM99:U0|TEMP[4]~343 SUM99:U0|TEMP[4] } "NODE_NAME" } } { "dds.vhd" "" { Text "c:/altera/70/quartus/dds/dds.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.872 ns ( 54.15 % ) " "Info: Total cell delay = 1.872 ns ( 54.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.585 ns ( 45.85 % ) " "Info: Total interconnect delay = 1.585 ns ( 45.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.457 ns" { K[4] SUM99:U0|TEMP[4]~343 SUM99:U0|TEMP[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.457 ns" { K[4] K[4]~combout SUM99:U0|TEMP[4]~343 SUM99:U0|TEMP[4] } { 0.000ns 0.000ns 1.585ns 0.000ns } { 0.000ns 1.140ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.787 ns" { CLK CLK~clkctrl SUM99:U0|TEMP[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.787 ns" { CLK CLK~combout CLK~clkctrl SUM99:U0|TEMP[4] } { 0.000ns 0.000ns 0.143ns 0.838ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.457 ns" { K[4] SUM99:U0|TEMP[4]~343 SUM99:U0|TEMP[4] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.457 ns" { K[4] K[4]~combout SUM99:U0|TEMP[4]~343 SUM99:U0|TEMP[4] } { 0.000ns 0.000ns 1.585ns 0.000ns } { 0.000ns 1.140ns 0.624ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}