CommandLineD:\Xilinx\10.1\ISE\bin\nt\unwrapped\map.exe -ise D:/Projects/verilog/New Folder/sequencedetector/sequencedetector.ise -intstyle ise -p xc3s200-ft256-4 -cm area -pr off -k 4 -c 100 -o seqdet_map.ncd seqdet.ngd seqdet.pcfsFormatStringmap <infile[.ngd]> [-bp] [-c [<packfactor:0,100>]] [-cm <covermode>] [-detail] [-equivalent_register_removal on|off] [-global_opt off|&speed|&area|on] [-ignore_keep_hierarchy] [-intstyle ise|xflow|silent] [-ir] [-ise <iseProjectFile>] [-k 4|5|6|7|8] [-l] [-lc off|area|auto] [-logic_opt off|on] [-ntd] [-o <outfile[.ncd]>] [-ol std|med|high] [-p <partname>] [-power off|on] [-activityfile <activityfile[.vcd|.saif]>] [-pr off|i|o|b] [-r] [-register_duplication [off|on]] [-retiming off|on] [-smartguide <guide[.ncd]>] [-t <costtable:1,100>] [-timing] [-tx on|off|aggressive|limit] [-u]  [-w]  [-x]  [-xe c|n] [--ds <doodlescript>] [--hv] [--lambda <inputlambda:1,15> <outputlambda:1,4>] [--m]  [--ms <mapscript>] [--physical_synthesis off|on] [--smartsynthesis <value>] [--ts_comb <combll> <combul>] [--ts_cy <cyll> <cyul>] [--ts_load <load>] [--ts_trigger <trigger>] [--use_soft_locs] [--global_opt_script <file>] [<prffile[.pcf]>]s