#add_file options
add_file -verilog "F:/FPGA大賽/FUSION STARTKIT (G)/實驗例程/高級實驗/LCD實驗/Project/LCD_1602/smartgen/PLL_1M/PLL_1M.v"
add_file -verilog "F:/FPGA大賽/FUSION STARTKIT (G)/實驗例程/高級實驗/LCD實驗/Project/LCD_1602/hdl/Clock_Gen.v"
add_file -verilog "F:/FPGA大賽/FUSION STARTKIT (G)/實驗例程/高級實驗/LCD實驗/Project/LCD_1602/hdl/LCD_Driver.v"
add_file -verilog "F:/FPGA大賽/FUSION STARTKIT (G)/實驗例程/高級實驗/LCD實驗/Project/LCD_1602/hdl/LCD_Top.v"
set_option -top_module LCD_Top

#device options
set_option -technology Fusion
set_option -part AFS600
set_option -vlog_std v2001

#compilation/mapping options
set_option -symbolic_fsm_compiler true

#compilation/mapping options
set_option -frequency 100.000

#simulation options
impl -active "synthesis"
project -result_file "F:/FPGA大賽/FUSION STARTKIT (G)/實驗例程/高級實驗/LCD實驗/Project/LCD_1602/synthesis/LCD_Top.edn"