//WatchDog counter

module watchdog(
	clk,
	rst_n,
	wdval,
	wden,
	wdi,
//	wdf,
	wdo
	);

	input clk,rst_n;
	input wden;//watchdog enable
	input wdi;//watchdog refresh
//	output wdf;//watchdog reset flag (hardware reset or write 1 clear this bit)
//	reg wdf;
	output wdo;//watchdog reset out
	reg wdo;
	input [6:0] wdval;

	wire [31:0] time1 = (wdval * 32'h01FCA055);//1s(f=33.333MHz)
	wire [31:0] time2 = (time1 + 32'h00001A0A);//200ms

	reg [31:0] counter;

always @(posedge clk or negedge rst_n)
	begin
	    if(!rst_n)
	    	begin
	    	    counter <= 32'b0;
	    	    wdo <= 1'b1;
	    	end
	    else if(!wden || wdi) counter <= 32'b0;
	    else
	        begin
	            counter <= counter + 1;
	            if(counter == time1) wdo <= 1'b0;
	            if(counter == time2) wdo <= 1'b1;
	        end
	end


endmodule