library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div8 is
port(clk2:in std_logic;      
         reset:in std_logic;
         C_ENB2:out std_logic;
         cout2:out std_logic);
end div8;

architecture behave of div8 is
signal cnt:std_logic_vector(2 downto 0);
begin
process(clk2,reset)
begin
if(reset='1')then
  cnt<="000";
  cout2<='0';
elsif(clk2'event and clk2='1')then
  cnt<=cnt+"001";
  cout2<=cnt(2);
  C_ENB2<=cnt(2)and cnt(1) and cnt(0);
end if;
end process;
end;