// $Id: DW8051_serial.v,v 1.1 1996/07/25 17:43:22 gina Exp $//------------------------------------------------------------------------------////        This confidential and proprietary software may be used only//     as authorized by a licensing agreement from Synopsys Inc.//     In the event of publication, the following notice is applicable:////                    (C) COPYRIGHT 1996   SYNOPSYS INC.//                          ALL RIGHTS RESERVED////        The entire notice above must be reproduced on all authorized//        copies.//// FILE: 	DW8051_serial.v//// AUTHOR:	Gregor Uhlaender//// ABSTRACT: 	DW8051 serial module (Verilog version)//// MODIFICATION HISTORY://      L.Rieder        28.05.96        Verilog version created////      Gina Ngo        11.20.96        Fixed star 38722: added header//      Bala Needamangalam//                      July 20,1999    Removed all DesignWare-Foundation //                                      license checkout commands.//------------------------------------------------------------------------------`include "./DW8051/DW8051_package.inc"`include "./DW8051/DW8051_parameter.v"module DW8051_serial (clk,                      rst_n,                      // sfr bus:                      sfr_addr,                      serial_sfr_cs,                      serial_data_out,                      serial_data_in,                      sfr_wr,                      // baudrate input from timer:                        t1_ofl,                      // baudrate inputs from timer2:                      rclk,                      tclk,                      t2_ofl,                      // signals from DW8051_cpu:                      cycle,                      smod,                      // signals to DW8051_intr                      ri,                      ti,                      // external IO:                      rxd_out,                      rxd_in,                      txd		      );parameter base_addr  = 1;  input clk; input rst_n; input [7:0]  sfr_addr; input [7:0]  serial_data_in; input sfr_wr; input t1_ofl; input rclk; input tclk; input t2_ofl; input [1:0]  cycle; input smod; input rxd_in; output serial_sfr_cs; output [7:0]  serial_data_out; output ri; output ti; output rxd_out; output txd;//------------------------------------------------------------------------------wire clk;wire rst_n;wire [7:0] sfr_addr;wire [7:0] serial_data_in;wire sfr_wr;wire t1_ofl;wire rclk;wire tclk;wire t2_ofl;wire [1:0] cycle;wire smod;wire rxd_in;wire serial_sfr_cs;wire [7:0] serial_data_out;wire ri;wire ti;reg  rxd_out;reg  txd;// type rx_state_type:`define rx_idle       2'b00`define rx_initialize 2'b01`define rx_transfer   2'b10`define rx_stop       2'b11// type tx_state_type:`define tx_idle         3'b000`define tx_initialize   3'b001`define tx_transfer_1st 3'b010`define tx_transfer     3'b011`define tx_stop1        3'b100`define tx_stop2        3'b101reg  [2:0] tx_state;reg  [1:0] rx_state; reg  [7:0] scon_reg;wire [1:0] mode;wire mode_change;wire mode0;wire mode1;wire mode2;wire mode3;wire mode1or3; wire sm2;wire ren;wire tb8;wire rb8;wire i_ti;wire i_ri; wire set_ti;wire rx_accept;reg  rx_update; wire scon_cs;wire sbuf_cs; wire legal_sbuf_wr;wire scon_wr; wire clk_div2;reg  clk_div12;wire sync_clk;reg  [1:0] count;  wire t_clk_x16;wire t_clk_x16_m2;reg  tx_m123_clk;wire tx_t_clk_x16;wire rx_t_clk_x16;		// sample clock for rxd_inwire rx_t_clk;reg  rxd_l0;			// latched rxd_inreg  rxd_l0b;reg  rxd_l1;			// latched rxd_l0reg  rxd_l2;			// latched rxd_l1reg  rxd_l3;			// latched rxd_l2wire rxd_event;			// set when high to low transition detected wire clr_rx_cnt_n;wire ld_tx_cnt_n; wire [3:0] rx_cnt;wire [3:0] tx_cnt; reg  store_t1_ofl; wire tx_ser_in;wire [1:0] tx_par_in_msb;wire [9:0] tx_par_in;wire [9:0] tx_par_in_rev;wire tx_load_n;wire tx_shift_n;wire [9:0] tx_sbuf_reg;wire [9:0] tx_reg_rev; wire rx_ser_in;wire [8:0] rx_par_in;wire [8:0] rx_par_in_rev;wire rx_load_n;wire rx_shift_n;wire [8:0] rx_reg;wire [8:0] rx_reg_rev;reg  [7:0] rx_sbuf_reg;wire rx_tercnt; wire rx_clk;wire tx_clk; wire tx_tercnt; wire zero_det_n; reg  shift_clk; wire tx_busy;wire rx_busy;wire port_busy; wire send;wire receive;wire data;wire stop_tx;wire stop_rx; wire rx_bit;wire rx_cmp_3; wire high;wire [3:0] low_4;wire [3:0] tx_ld_data; reg  ti_just_set;reg  ri_just_set;wire [7:0] base_addr_p_1;//------------------------------------------------------------------------------  // define constant signals  assign  high       = 1;  assign  low_4      = 'b0;  assign  tx_ld_data = 4'b1111;  assign base_addr_p_1 = (base_addr + 1);  // sfr registers:  assign  mode = scon_reg[7:6];  assign  sm2  = scon_reg[5];  assign  ren  = scon_reg[4];  assign  tb8  = scon_reg[3];  assign  rb8  = scon_reg[2];  assign  i_ti = scon_reg[1];  assign  i_ri = scon_reg[0];  assign scon_cs  = (sfr_addr ==  base_addr)    ? 1 : 0;  assign sbuf_cs  = (sfr_addr == base_addr_p_1) ? 1 : 0;  // decode mode  assign  mode0    = ~(mode[0] |  mode[1]);  assign  mode1    =   mode[0] & ~mode[1];  assign  mode2    =  ~mode[0] &  mode[1];  assign  mode3    =   mode[0] &  mode[1];  assign  mode1or3 =   mode[0];  assign tx_busy    = (tx_state != `tx_idle) ? 1 : 0;  assign rx_busy    = (rx_state != `rx_idle) ? 1 : 0;  assign port_busy  = tx_busy | rx_busy;  assign  legal_sbuf_wr = sbuf_cs & sfr_wr & ~tx_busy;  assign  scon_wr = scon_cs & sfr_wr;  always @(posedge clk or negedge rst_n)  begin : sfr_process    if (rst_n == 0)    begin       scon_reg    <= 'b0;      rx_sbuf_reg <= 'b0;      ti_just_set <= 0;      ri_just_set <= 0;    end    else    begin      if (cycle == `c3)      begin         ti_just_set  <= set_ti;        if (mode0 == 1) ri_just_set <= rx_accept;      end       // scon register           if (rx_accept == 1) scon_reg[0] <= 1;      else if ((scon_wr == 1) & (ri_just_set == 0))                               scon_reg[0] <= serial_data_in[0];           if (set_ti == 1)    scon_reg[1] <= 1;      else if ((scon_wr == 1) & (ti_just_set == 0))                               scon_reg[1] <= serial_data_in[1];           if ((rx_accept == 1) & (mode0 == 0))                               scon_reg[2] <= rx_bit;      else if (scon_wr == 1)   scon_reg[2] <= serial_data_in[2];      if (scon_wr == 1)   scon_reg[7:3] <= serial_data_in[7:3];      // rx_sbuf register      if (rx_update == 1) rx_sbuf_reg   <= rx_reg[7:0];     end   end  //sfr_process  assign tx_load_n      = ~legal_sbuf_wr;  assign tx_par_in_msb  = ((mode0 == 1) | (mode1 == 1)) ? 2'b01 :                                                          {1'b1, tb8};  assign  tx_par_in     = {tx_par_in_msb, serial_data_in};  //----------------------------------------------------------------------------  // tx shift register:  DW8051_shftreg #(10) u0                    (.clk     (clk),                     .s_in    (tx_ser_in),                     .p_in    (tx_par_in_rev),                     .shift_n (tx_shift_n),                     .load_n  (tx_load_n),                     .reset_n (rst_n),                     .p_out   (tx_reg_rev));  // reverse order of bits: DW8051_shftreg assumes MSB first  //                        but data are transmitted LSB first  assign  tx_par_in_rev[0] = tx_par_in[9];  assign  tx_par_in_rev[1] = tx_par_in[8];  assign  tx_par_in_rev[2] = tx_par_in[7];  assign  tx_par_in_rev[3] = tx_par_in[6];  assign  tx_par_in_rev[4] = tx_par_in[5];  assign  tx_par_in_rev[5] = tx_par_in[4];  assign  tx_par_in_rev[6] = tx_par_in[3];  assign  tx_par_in_rev[7] = tx_par_in[2];  assign  tx_par_in_rev[8] = tx_par_in[1];  assign  tx_par_in_rev[9] = tx_par_in[0];  assign  tx_sbuf_reg[0]   = tx_reg_rev[9];  assign  tx_sbuf_reg[1]   = tx_reg_rev[8];  assign  tx_sbuf_reg[2]   = tx_reg_rev[7];  assign  tx_sbuf_reg[3]   = tx_reg_rev[6];  assign  tx_sbuf_reg[4]   = tx_reg_rev[5];  assign  tx_sbuf_reg[5]   = tx_reg_rev[4];  assign  tx_sbuf_reg[6]   = tx_reg_rev[3];  assign  tx_sbuf_reg[7]   = tx_reg_rev[2];  assign  tx_sbuf_reg[8]   = tx_reg_rev[1];  assign  tx_sbuf_reg[9]   = tx_reg_rev[0];  // rx shift register:  DW8051_shftreg #(9) u1                   (.clk     (clk),                    .s_in    (rx_ser_in),                    .p_in    (rx_par_in_rev),                    .shift_n (rx_shift_n),                    .load_n  (rx_load_n),                    .reset_n (rst_n),                    .p_out   (rx_reg_rev));  // reverse order of bits: DW8051_shftreg assumes MSB first  //                        but data are received LSB first  assign  rx_par_in_rev[0] = rx_par_in[8];  assign  rx_par_in_rev[1] = rx_par_in[7];  assign  rx_par_in_rev[2] = rx_par_in[6];  assign  rx_par_in_rev[3] = rx_par_in[5];  assign  rx_par_in_rev[4] = rx_par_in[4];  assign  rx_par_in_rev[5] = rx_par_in[3];  assign  rx_par_in_rev[6] = rx_par_in[2];  assign  rx_par_in_rev[7] = rx_par_in[1];  assign  rx_par_in_rev[8] = rx_par_in[0];  assign  rx_reg[0] = rx_reg_rev[8];  assign  rx_reg[1] = rx_reg_rev[7];  assign  rx_reg[2] = rx_reg_rev[6];  assign  rx_reg[3] = rx_reg_rev[5];  assign  rx_reg[4] = rx_reg_rev[4];  assign  rx_reg[5] = rx_reg_rev[3];  assign  rx_reg[6] = rx_reg_rev[2];  assign  rx_reg[7] = rx_reg_rev[1];  assign  rx_reg[8] = rx_reg_rev[0];  //----------------------------------------------------------------------------