?? dw8051_op_decoder.v
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// $Id: DW8051_op_decoder.v,v 1.1 1996/07/25 17:43:07 gina Exp $//------------------------------------------------------------------------------//// This confidential and proprietary software may be used only// as authorized by a licensing agreement from Synopsys Inc.// In the event of publication, the following notice is applicable://// (C) COPYRIGHT 1996 SYNOPSYS INC.// ALL RIGHTS RESERVED//// The entire notice above must be reproduced on all authorized// copies.//// FILE: DW8051_op_decoder.v//// AUTHOR: Ludwig Rieder//// ABSTRACT: DW8051 instruction decoder (Verilog version)//// MODIFICATION HISTORY:// L.Rieder 28.05.96 Verilog version created//// Gina Ngo 11.20.96 Fixed star 38722: added header// Bala Needamangalam// May 20,1998 Removed Blocking assignments for// oph and opl. Changed all references to// oph/opl to the actual op[a:b]// dereferences.// July 20,1999 Removed all DesignWare-Foundation // license checkout commands.//------------------------------------------------------------------------------`include "./DW8051/DW8051_package.inc"`include "./DW8051/DW8051_parameter.v"module DW8051_op_decoder (op, int, idle_mode_n, itype, last_cycle, src, src_cycle, dest, alu_op, chg_flags, rmw ); input [7:0] op; input int; input idle_mode_n; output [4:0] itype; // 0..31 output [2:0] last_cycle; // 0..7 output [3:0] src; // 0..15 output [1:0] src_cycle; // 0..3 output [3:0] dest; // 0..15 output [5:0] alu_op; output chg_flags; output rmw;//------------------------------------------------------------------------------// DESCRIPTION//------------------------------------------------------------------------------//// src dest// 1 accumulator 1 accumulator// 2 register Rn 2 register Rn// 3 direct data (2nd cycle) 3 direct data (type 1)// 4 indirect @Ri (1Byte) 4 indirect @Ri (1Byte)// 5 #data 5 accu direct// 6 ext RAM, @Ri 6 ext.RAM, @Ri// 7 bit 7 bit// 8 8 direct (type 2)// 9 9 direct (type 3)// 10 10 indirect (type 2)// 11 11 indirect (type 3)// 12 @SP 12 @SP// 13 13 dptr (src instr)// 14 ROM 14 dptr (src add16_sum)// 15 ext.RAM, @DPTR 15 ext.RAM, @DPTR////// instruction type//// One Machine-Cycle instructions:// 0 none (default after reset)// 0 NOP// 1 RR A, INC A, INC @Ri, INC Rn, RRC A, DEC A, DEC @Ri, DEC Rn,// RL A, RLC A, CPL C, CLR C, SWAP A, SETB C, DA A, CLR A,// MOV A,@Ri, MOV A,Rn, CPL A, MOV @Ri,A, MOV Rn,A// 1 XCH A,@Ri, XCH A,Rn, XCHD A,@Ri// 2 idle_mode// 3 ADD A,@Ri, ADD A,Rn, ADDC A,@Ri, ADDC A,Rn, ORL A,@Ri, ORL A,Rn,// ANL A,@Ri, ANL A,Rn, XRL A,@Ri, XRL A,Rn, SUBB A,@Ri, SUBB A,Rn//// Two Machine-Cycle instructions:// 4 ADD A,#data, ADD A,direct, ADDC A,#data, ADDC A,direct,// ORL direct,A, ORL A,#data, ORL A,direct, ANL direct,A,// ANL A,#data, ANL A,direct, XRL direct,A, XRL A,#data,// XRL A,direct, SUBB A,#data, SUBB A,direct// 5 INC direct, DEC direct, MOV A,#data, MOV @Ri,#data,// MOV Rn,#data, MOV direct,@Ri, MOV direct,Rn, MOV bit,C,// MOV @Ri,direct, MOV Rn,direct, CPL bit, CLR bit, SETB bit,// MOV A,direct, MOV direct,A// 5 XCH A,direct// 6 ORL C,bit, ANL C,bit, ORL C,/bit, MOV C,bit, ANL C,/bit// 7 PUSH, POP// 8 MOVX A,@DPTR, MOVX A,@Ri, MOVX @DPTR,A, MOVX @Ri,A//// Three Machine-Cycle instructions:// 9 MOV direct,direct// 10 MOV direct,#data// 11 ORL direct,#data, ANL direct,#data, XRL direct,#data// 12 INC DPTR// 13 DJNZ Rn,rel// 14 ACALL// 15 AJMP// 16 SJMP// 17 JMP @A+DPTR// 18 JC,JNC,JZ,JNZ// 19 MOVC A,@A+PC, MOVC A,@A+DPTR// 20 MOV DPTR,#data//// Four Machine-Cycle instructions:// 21 JBC, JB, JNB// 22 CJNE A,#data,rel, CJNE A,direct,rel CJNE @Ri,#data,rel,// CJNE Rn,#data,rel// 23 LCALL// 24 LJMP// 25 RET// 25 RETI// 26 DJNZ direct,rel// 27 interrupts//// Five Machine-Cycle instructions:// 28 MUL AB// 29 DIV AB////// itypes NOT used: 30,31//// opcode type src dest rmw Bytes mnem. operands// Code/Ex// 0000_0000 0 - - - 1/1 NOP -// 0000_0001 15 - - - 2/3 AJMP code addr// 0000_0010 24 - - - 3/4 LJMP code addr// 0000_0011 1 1 1 - 1/1 RR A// 0000_0100 1 1 1 - 1/1 INC A// 0000_0101 5 3 3 1 2/2 INC direct// 0000_011x 1 4 4 - 1/1 INC @Ri// 0000_1xxx 1 2 2 - 1/1 INC Rn//// 0001_0000 21 7 7 1 3/4 JBC bit addr,code addr// 0001_0001 14 - - - 2/3 ACALL code addr// 0001_0010 23 - - - 3/4 LCALL code addr// 0001_0011 1 1 1 - 1/1 RRC A// 0001_0100 1 1 1 - 1/1 DEC A// 0001_0101 5 3 3 1 2/2 DEC direct// 0001_011x 1 4 4 - 1/1 DEC @Ri// 0001_1xxx 1 2 2 - 1/1 DEC Rn//// 0010_0000 21 7 - - 3/4 JB bit addr,code addr// 0010_0001 15 - - - 2/3 AJMP code addr// 0010_0010 25 - - - 1/4 RET// 0010_0011 1 1 1 - 1/1 RL A// 0010_0100 4 5 1 - 2/2 ADD A,#data// 0010_0101 4 3 1 - 2/2 ADD A,direct// 0010_011x 3 4 1 - 1/1 ADD A,@Ri// 0010_1xxx 3 2 1 - 1/1 ADD A,Rn//// 0011_0000 21 7 - - 3/4 JNB bit,addr,code// 0011_0001 14 - - - 2/3 ACALL addr// 0011_0010 25 - - - 1/4 RETI (code addr)// 0011_0011 1 1 1 - 1/1 RLC A// 0011_0100 4 5 1 - 2/2 ADDC A,#data// 0011_0101 4 3 1 - 2/2 ADDC A,direct// 0011_011x 3 4 1 - 1/1 ADDC A,@Ri// 0011_1xxx 3 2 1 - 1/1 ADDC A,Rn//// 0100_0000 18 - - - 2/3 JC code addr// 0100_0001 15 - - - 2/3 AJMP code addr// 0100_0010 4 3 3 1 2/2 ORL direct,A// 0100_0011 11 3 8 1 3/3 ORL direct,#data// 0100_0100 4 5 1 - 2/2 ORL A,#data// 0100_0101 4 3 1 - 2/2 ORL A,direct// 0100_011x 3 4 1 - 1/1 ORL A,@Ri// 0100_1xxx 3 2 1 - 1/1 ORL A,Rn//// 0101_0000 18 - - - 2/3 JNC code addr// 0101_0001 14 - - - 2/3 ACALL code addr// 0101_0010 4 3 3 1 2/2 ANL direct,A// 0101_0011 11 3 8 1 3/3 ANL direct,#data// 0101_0100 4 5 1 - 2/2 ANL A,#data// 0101_0101 4 3 1 - 2/2 ANL A,direct// 0101_011x 3 4 1 - 1/1 ANL A,@Ri// 0101_1xxx 3 2 1 - 1/1 ANL A,Rn//// 0110_0000 18 1 - - 2/3 JZ code addr// 0110_0001 15 - - - 2/3 AJMP code addr// 0110_0010 4 3 3 1 2/2 XRL direct,A// 0110_0011 11 3 8 1 3/3 XRL direct,#data// 0110_0100 4 5 1 - 2/2 XRL A,#data// 0110_0101 4 3 1 - 2/2 XRL A,direct// 0110_011x 3 4 1 - 1/1 XRL A,@Ri// 0110_1xxx 3 2 1 - 1/1 XRL A,Rn//// 0111_0000 18 1 - - 2/3 JNZ code addr// 0111_0001 14 - - - 2/3 ACALL code addr// 0111_0010 6 7 - - 2/2 ORL C,bit addr// 0111_0011 17 - - - 1/3 JMP @A+DPTR// 0111_0100 5 5 1 - 2/2 MOV A,#data// 0111_0101 10 5 8 - 3/3 MOV direct,#data// 0111_011x 5 5 4 - 2/2 MOV @Ri,#data// 0111_1xxx 5 5 2 - 2/2 MOV Rn,#data//// 1000_0000 16 - - - 2/3 SJMP code addr// 1000_0001 15 - - - 2/3 AJMP code addr// 1000_0010 6 7 - - 2/2 ANL C,bit// 1000_0011 19 14 5 - 1/3 MOVC A,@A+PC// 1000_0100 29 - - - 1/5 DIV AB// 1000_0101 9 3 3 - 3/3 MOV direct,direct// 1000_011x 5 4 3 - 2/2 MOV direct,@Ri// 1000_1xxx 5 2 3 - 2/2 MOV direct,Rn//// 1001_0000 20 - 13 - 3/3 MOV DPTR,#data// 1001_0001 14 - - - 2/3 ACALL code addr// 1001_0010 5 7 7 1 2/2 MOV bit,C// 1001_0011 19 14 5 - 1/3 MOVC A,@A+DPTR// 1001_0100 4 5 1 - 2/2 SUBB A,#data// 1001_0101 4 3 1 - 2/2 SUBB A,direct// 1001_011x 3 4 1 - 1/1 SUBB A,@Ri// 1001_1xxx 3 2 1 - 1/1 SUBB A,Rn//// 1010_0000 6 7 - - 2/2 ORL C,/bit// 1010_0001 15 - - - 2/3 AJMP code addr// 1010_0010 6 7 - - 2/2 MOV C,bit// 1010_0011 12 - 14 - 1/3 INC DPTR// 1010_0100 28 - - - 1/5 MUL AB// 1010_0101 0 - - - - reserved (-> NOP)// 1010_011x 5 3 4 - 2/2 MOV @Ri,direct// 1010_1xxx 5 3 2 - 2/2 MOV Rn,direct//// 1011_0000 6 7 - - 2/2 ANL C,/bit// 1011_0001 14 - - - 2/3 ACALL code addr// 1011_0010 5 7 7 1 2/2 CPL bit// 1011_0011 1 - - - 1/1 CPL C// 1011_0100 22 1 - - 3/4 CJNE A,#data,rel// 1011_0101 22 1 - - 3/4 CJNE A,direct,rel// 1011_011x 22 4 - - 3/4 CJNE @Ri,#data,rel// 1011_1xxx 22 2 - - 3/4 CJNE Rn,#data,rel//// 1100_0000 7 3 12 - 2/2 PUSH direct// 1100_0001 15 - - - 2/3 AJMP code addr// 1100_0010 5 7 7 1 2/2 CLR bit// 1100_0011 1 - - - 1/1 CLR C// 1100_0100 1 1 1 - 1/1 SWAP A// 1100_0101 5 3 9 - 2/2 XCH A,direct// 1100_011x 1 4 10 - 1/1 XCH A,@Ri// 1100_1xxx 1 2 9 - 1/1 XCH A,Rn////// 0111_0000 18 1 - - 2/3 JNZ code addr// 0111_0001 14 - - - 2/3 ACALL code addr// 0111_0010 6 7 - - 2/2 ORL C,bit addr// 0111_0011 17 - - - 1/3 JMP @A+DPTR// 0111_0100 5 5 1 - 2/2 MOV A,#data// 0111_0101 10 5 8 - 3/3 MOV direct,#data// 0111_011x 5 5 4 - 2/2 MOV @Ri,#data// 0111_1xxx 5 5 2 - 2/2 MOV Rn,#data//// 1000_0000 16 - - - 2/3 SJMP code addr// 1000_0001 15 - - - 2/3 AJMP code addr// 1000_0010 6 7 - - 2/2 ANL C,bit// 1000_0011 19 14 5 - 1/3 MOVC A,@A+PC// 1000_0100 29 - - - 1/5 DIV AB// 1000_0101 9 3 3 - 3/3 MOV direct,direct// 1000_011x 5 4 3 - 2/2 MOV direct,@Ri// 1000_1xxx 5 2 3 - 2/2 MOV direct,Rn//// 1001_0000 20 - 13 - 3/3 MOV DPTR,#data// 1001_0001 14 - - - 2/3 ACALL code addr// 1001_0010 5 7 7 1 2/2 MOV bit,C// 1001_0011 19 14 5 - 1/3 MOVC A,@A+DPTR// 1001_0100 4 5 1 - 2/2 SUBB A,#data// 1001_0101 4 3 1 - 2/2 SUBB A,direct// 1001_011x 3 4 1 - 1/1 SUBB A,@Ri// 1001_1xxx 3 2 1 - 1/1 SUBB A,Rn//// 1010_0000 6 7 - - 2/2 ORL C,/bit// 1010_0001 15 - - - 2/3 AJMP code addr// 1010_0010 6 7 - - 2/2 MOV C,bit// 1010_0011 12 - 14 - 1/3 INC DPTR// 1010_0100 28 - - - 1/5 MUL AB// 1010_0101 0 - - - - reserved (-> NOP)// 1010_011x 5 3 4 - 2/2 MOV @Ri,direct// 1010_1xxx 5 3 2 - 2/2 MOV Rn,direct//// 1011_0000 6 7 - - 2/2 ANL C,/bit// 1011_0001 14 - - - 2/3 ACALL code addr// 1011_0010 5 7 7 1 2/2 CPL bit// 1011_0011 1 - - - 1/1 CPL C// 1011_0100 22 1 - - 3/4 CJNE A,#data,rel// 1011_0101 22 1 - - 3/4 CJNE A,direct,rel// 1011_011x 22 4 - - 3/4 CJNE @Ri,#data,rel// 1011_1xxx 22 2 - - 3/4 CJNE Rn,#data,rel//// 1100_0000 7 3 12 - 2/2 PUSH direct// 1100_0001 15 - - - 2/3 AJMP code addr// 1100_0010 5 7 7 1 2/2 CLR bit// 1100_0011 1 - - - 1/1 CLR C// 1100_0100 1 1 1 - 1/1 SWAP A// 1100_0101 5 3 9 - 2/2 XCH A,direct?? 快捷鍵說明
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