library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity yuv is port(
y1,u,v,y2: in std_logic_vector(7 downto 0);
r1,g1,b1: out std_logic_vector(1 downto 0);
r2,g2,b2: out std_logic_vector(1 downto 0));
end yuv;

architecture yuv_arq of yuv is

signal k: signed(9 downto 0);
signal ye1,ye2,ue,ve: signed(9 downto 0);
signal cy,c1,c2,c3,c4,c5,c6: signed(9 downto 0);
signal m1,m2,m3,m4,m5,m6,my1,my2: signed(19 downto 0);
signal re1,ge1,be1: signed(19 downto 0);
signal re2,ge2,be2: signed(19 downto 0);
signal auxy1,auxy2,auxu,auxv : signed(9 downto 0);

begin
k<="0010000000";
auxy1(9 downto 8)<="00";
auxy2(9 downto 8)<="00";
auxu(9 downto 8)<="00";
auxv(9 downto 8)<="00";
auxy1(7 downto 0)<=signed(y1);
auxy2(7 downto 0)<=signed(y2);
auxu(7 downto 0)<=signed(u);
auxv(7 downto 0)<=signed(v);
ye1<=auxy1;
ye2<=auxy2;
ue<=auxu-k;
ve<=auxv-k;

cy<="0100000000"; --(256)
c1<="0000000000"; --(0)
c2<="0101011110"; --(350)
c3<="1110101011"; --(-85)
c4<="1101001101"; --(-179)
c5<="0110111011"; --(443)
c6<="1111111111"; --(-1)

my1<=cy*ye1;
my2<=cy*ye2;
m1<=c1*ue;
m2<=c2*ve;
m3<=c3*ue;
m4<=c4*ve;
m5<=c5*ue;
m6<=c6*ve;

re1<=my1+m1+m2;
ge1<=my1+m3+m4;
be1<=my1+m5+m6;

re2<=my2+m1+m2;
ge2<=my2+m3+m4;
be2<=my2+m5+m6;

r1<=CONV_STD_LOGIC_VECTOR(re1(15 downto 14),2);
g1<=CONV_STD_LOGIC_VECTOR(ge1(15 downto 14),2);
b1<=CONV_STD_LOGIC_VECTOR(be1(15 downto 14),2);

r2<=CONV_STD_LOGIC_VECTOR(re2(15 downto 14),2);
g2<=CONV_STD_LOGIC_VECTOR(ge2(15 downto 14),2);
b2<=CONV_STD_LOGIC_VECTOR(be2(15 downto 14),2);


end yuv_arq;