/* system.h * * Machine generated for a CPU named "cpu_0" as defined in: * D:\Test\C12_SD\software\C20_BGA_SD_syslib\..\..\Nios.ptf * * Generated: 2007-04-03 15:16:31.687 * */#ifndef __SYSTEM_H_#define __SYSTEM_H_/*DO NOT MODIFY THIS FILE   Changing this file will have subtle consequences   which will almost certainly lead to a nonfunctioning   system. If you do modify this file, be aware that your   changes will be overwritten and lost when this file   is generated again.DO NOT MODIFY THIS FILE*//*******************************************************************************                                                                             ** License Agreement                                                           **                                                                             ** Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           ** All rights reserved.                                                        **                                                                             ** Permission is hereby granted, free of charge, to any person obtaining a     ** copy of this software and associated documentation files (the "Software"),  ** to deal in the Software without restriction, including without limitation   ** the rights to use, copy, modify, merge, publish, distribute, sublicense,    ** and/or sell copies of the Software, and to permit persons to whom the       ** Software is furnished to do so, subject to the following conditions:        **                                                                             ** The above copyright notice and this permission notice shall be included in  ** all copies or substantial portions of the Software.                         **                                                                             ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  ** IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    ** FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ** AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      ** LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     ** FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         ** DEALINGS IN THE SOFTWARE.                                                   **                                                                             ** This agreement shall be governed in all respects by the laws of the State   ** of California and by the laws of the United States of America.              **                                                                             *******************************************************************************//* * system configuration * */#define ALT_SYSTEM_NAME "Nios"#define ALT_CPU_NAME "cpu_0"#define ALT_CPU_ARCHITECTURE "altera_nios2"#define ALT_DEVICE_FAMILY "CYCLONEII"#define ALT_STDIN "/dev/uart_0"#define ALT_STDOUT "/dev/uart_0"#define ALT_STDERR "/dev/uart_0"#define ALT_CPU_FREQ 50000000#define ALT_IRQ_BASE NULL/* * processor configuration * */#define NIOS2_CPU_IMPLEMENTATION "tiny"#define NIOS2_ICACHE_SIZE 0#define NIOS2_DCACHE_SIZE 0#define NIOS2_ICACHE_LINE_SIZE 0#define NIOS2_ICACHE_LINE_SIZE_LOG2 0#define NIOS2_DCACHE_LINE_SIZE 0#define NIOS2_DCACHE_LINE_SIZE_LOG2 0#define NIOS2_FLUSHDA_SUPPORTED#define NIOS2_EXCEPTION_ADDR 0x00004020#define NIOS2_RESET_ADDR 0x00004000#define NIOS2_HAS_DEBUG_STUB#define NIOS2_CPU_ID_SIZE 1#define NIOS2_CPU_ID_VALUE 0/* * A define for each class of peripheral * */#define __ALTERA_AVALON_JTAG_UART#define __ALTERA_AVALON_SPI#define __ALTERA_AVALON_ONCHIP_MEMORY2#define __ALTERA_AVALON_PIO#define __ALTERA_AVALON_UART/* * jtag_uart_0 configuration * */#define JTAG_UART_0_NAME "/dev/jtag_uart_0"#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"#define JTAG_UART_0_BASE 0x00000800#define JTAG_UART_0_SPAN 8#define JTAG_UART_0_IRQ 0#define JTAG_UART_0_WRITE_DEPTH 64#define JTAG_UART_0_READ_DEPTH 64#define JTAG_UART_0_WRITE_THRESHOLD 8#define JTAG_UART_0_READ_THRESHOLD 8#define JTAG_UART_0_READ_CHAR_STREAM ""#define JTAG_UART_0_SHOWASCII 1#define JTAG_UART_0_READ_LE 0#define JTAG_UART_0_WRITE_LE 0#define JTAG_UART_0_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0/* * spi_0 configuration * */#define SPI_0_NAME "/dev/spi_0"#define SPI_0_TYPE "altera_avalon_spi"#define SPI_0_BASE 0x00000820#define SPI_0_SPAN 32#define SPI_0_IRQ 1#define SPI_0_DATABITS 8#define SPI_0_TARGETCLOCK 128#define SPI_0_CLOCKUNITS "kHz"#define SPI_0_CLOCKMULT 1000#define SPI_0_NUMSLAVES 1#define SPI_0_ISMASTER 1#define SPI_0_CLOCKPOLARITY 0#define SPI_0_CLOCKPHASE 0#define SPI_0_LSBFIRST 0#define SPI_0_EXTRADELAY 0#define SPI_0_TARGETSSDELAY 100#define SPI_0_DELAYUNITS "us"#define SPI_0_DELAYMULT "1e-006"#define SPI_0_CLOCKUNIT "kHz"#define SPI_0_DELAYUNIT "us"#define SPI_0_PREFIX "spi_"/* * onchip_memory_0 configuration * */#define ONCHIP_MEMORY_0_NAME "/dev/onchip_memory_0"#define ONCHIP_MEMORY_0_TYPE "altera_avalon_onchip_memory2"#define ONCHIP_MEMORY_0_BASE 0x00004000#define ONCHIP_MEMORY_0_SPAN 16384#define ONCHIP_MEMORY_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0#define ONCHIP_MEMORY_0_RAM_BLOCK_TYPE "M4K"#define ONCHIP_MEMORY_0_INIT_CONTENTS_FILE "onchip_memory_0"#define ONCHIP_MEMORY_0_NON_DEFAULT_INIT_FILE_ENABLED 0#define ONCHIP_MEMORY_0_GUI_RAM_BLOCK_TYPE "Automatic"#define ONCHIP_MEMORY_0_WRITEABLE 1#define ONCHIP_MEMORY_0_DUAL_PORT 0#define ONCHIP_MEMORY_0_SIZE_VALUE 16#define ONCHIP_MEMORY_0_SIZE_MULTIPLE 1024#define ONCHIP_MEMORY_0_CONTENTS_INFO "QUARTUS_PROJECT_DIR/onchip_memory_0.hex 1174743890"/* * SD_PWR configuration * */#define SD_PWR_NAME "/dev/SD_PWR"#define SD_PWR_TYPE "altera_avalon_pio"#define SD_PWR_BASE 0x00000810#define SD_PWR_SPAN 16#define SD_PWR_DO_TEST_BENCH_WIRING 0#define SD_PWR_DRIVEN_SIM_VALUE 0x0000#define SD_PWR_HAS_TRI 0#define SD_PWR_HAS_OUT 1#define SD_PWR_HAS_IN 0#define SD_PWR_CAPTURE 0#define SD_PWR_EDGE_TYPE "NONE"#define SD_PWR_IRQ_TYPE "NONE"#define SD_PWR_FREQ 50000000/* * SD_CS configuration * */#define SD_CS_NAME "/dev/SD_CS"#define SD_CS_TYPE "altera_avalon_pio"#define SD_CS_BASE 0x00000840#define SD_CS_SPAN 16#define SD_CS_DO_TEST_BENCH_WIRING 0#define SD_CS_DRIVEN_SIM_VALUE 0x0000#define SD_CS_HAS_TRI 0#define SD_CS_HAS_OUT 1#define SD_CS_HAS_IN 0#define SD_CS_CAPTURE 0#define SD_CS_EDGE_TYPE "NONE"#define SD_CS_IRQ_TYPE "NONE"#define SD_CS_FREQ 50000000/* * uart_0 configuration * */#define UART_0_NAME "/dev/uart_0"#define UART_0_TYPE "altera_avalon_uart"#define UART_0_BASE 0x00000860#define UART_0_SPAN 32#define UART_0_IRQ 2#define UART_0_BAUD 115200#define UART_0_DATA_BITS 8#define UART_0_FIXED_BAUD 1#define UART_0_PARITY 'N'#define UART_0_STOP_BITS 1#define UART_0_USE_CTS_RTS 0#define UART_0_USE_EOP_REGISTER 0#define UART_0_SIM_TRUE_BAUD 0#define UART_0_SIM_CHAR_STREAM ""#define UART_0_FREQ 50000000/* * system library configuration * */#define ALT_MAX_FD 4#define ALT_SYS_CLK none#define ALT_TIMESTAMP_CLK none/* * Devices associated with code sections. * */#define ALT_TEXT_DEVICE       ONCHIP_MEMORY_0#define ALT_RODATA_DEVICE     ONCHIP_MEMORY_0#define ALT_RWDATA_DEVICE     ONCHIP_MEMORY_0#define ALT_EXCEPTIONS_DEVICE ONCHIP_MEMORY_0#define ALT_RESET_DEVICE      ONCHIP_MEMORY_0/* * The text section is initialised so no bootloader will be required. * Set a variable to tell crt0.S to provide code at the reset address and * to initialise rwdata if appropriate. */#define ALT_NO_BOOTLOADER#endif /* __SYSTEM_H_ */