?? sdram_tb.map.rpt
字號:
; state_r.initpchg ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; state_r.initsetmode ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; state_r.initrfsh ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; state_r.rw ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; state_r.activate ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state_r.refreshrow ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state_r.selfrefresh ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+---------------------+---------------------+--------------------+------------------+------------+------------------+---------------------+------------------+------------------+
+--------------------------------------------------------------------------------------------------------+
; State Machine - |sdram_tb|memTest:memt|state_r ;
+--------------------+--------------+--------------------+-----------------+--------------+--------------+
; Name ; state_r.stop ; state_r.empty_pipe ; state_r.compare ; state_r.load ; state_r.init ;
+--------------------+--------------+--------------------+-----------------+--------------+--------------+
; state_r.init ; 0 ; 0 ; 0 ; 0 ; 0 ;
; state_r.load ; 0 ; 0 ; 0 ; 1 ; 1 ;
; state_r.compare ; 0 ; 0 ; 1 ; 0 ; 1 ;
; state_r.empty_pipe ; 0 ; 1 ; 0 ; 0 ; 1 ;
; state_r.stop ; 1 ; 0 ; 0 ; 0 ; 1 ;
+--------------------+--------------+--------------------+-----------------+--------------+--------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 225 ;
; Number of registers using Synchronous Clear ; 37 ;
; Number of registers using Synchronous Load ; 19 ;
; Number of registers using Asynchronous Clear ; 151 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 110 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; sdramCntl:sdram1|cmd_r[6] ; 1 ;
; sdramCntl:sdram1|cmd_r[5] ; 1 ;
; sdramCntl:sdram1|cmd_r[4] ; 1 ;
; sdramCntl:sdram1|refTimer_r[9] ; 2 ;
; sdramCntl:sdram1|refTimer_r[8] ; 2 ;
; sdramCntl:sdram1|refTimer_r[3] ; 2 ;
; sdramCntl:sdram1|refTimer_r[2] ; 2 ;
; sdramCntl:sdram1|refTimer_r[1] ; 2 ;
; Total number of inverted registers = 8 ; ;
+----------------------------------------+---------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |sdram_tb|sdramCntl:sdram1|rasTimer_r[0] ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |sdram_tb|sdramCntl:sdram1|sAddr_r[5] ;
; 7:1 ; 13 bits ; 52 LEs ; 26 LEs ; 26 LEs ; Yes ; |sdram_tb|sdramCntl:sdram1|rfshCntr_r[3] ;
; 9:1 ; 23 bits ; 138 LEs ; 23 LEs ; 115 LEs ; Yes ; |sdram_tb|memTest:memt|addr_r[5] ;
; 9:1 ; 6 bits ; 36 LEs ; 18 LEs ; 18 LEs ; Yes ; |sdram_tb|sdramCntl:sdram1|timer_r[13] ;
; 10:1 ; 2 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |sdram_tb|sdramCntl:sdram1|timer_r[1] ;
; 4:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |sdram_tb|sdramCntl:sdram1|timer_x~85 ;
; 9:1 ; 3 bits ; 18 LEs ; 12 LEs ; 6 LEs ; No ; |sdram_tb|memTest:memt|state_r~3 ;
; 12:1 ; 2 bits ; 16 LEs ; 8 LEs ; 8 LEs ; No ; |sdram_tb|memTest:memt|state_r~4 ;
; 11:1 ; 3 bits ; 21 LEs ; 12 LEs ; 9 LEs ; No ; |sdram_tb|sdramCntl:sdram1|state_x.initsetmode ;
; 12:1 ; 2 bits ; 16 LEs ; 8 LEs ; 8 LEs ; No ; |sdram_tb|sdramCntl:sdram1|state_x.rw ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+
+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |sdram_tb ;
+----------------------+-------+-------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------------+-------+-------------------------------------------+
; freq ; 50000 ; Integer ;
; in_phase ; true ; Enumerated ;
; pipe_en ; false ; Enumerated ;
; max_nop ; 10000 ; Integer ;
; multiple_active_rows ; false ; Enumerated ;
; data_width ; 32 ; Integer ;
; nrows ; 4096 ; Integer ;
; ncols ; 256 ; Integer ;
; haddr_width ; 23 ; Integer ;
; addr_width ; 23 ; Integer ;
; saddr_width ; 12 ; Integer ;
+----------------------+-------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------+
; Parameter Settings for User Entity Instance: memTest:memt ;
+----------------+---------+--------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+---------+--------------------------------+
; pipe_en ; false ; Enumerated ;
; data_width ; 32 ; Integer ;
; addr_width ; 23 ; Integer ;
; beg_test ; 0 ; Integer ;
; end_test ; 4194303 ; Integer ;
+----------------+---------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: memTest:memt|randGen:u0 ;
+----------------+-------+---------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------------------+
; data_width ; 32 ; Integer ;
+----------------+-------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sdramCntl:sdram1 ;
+----------------------+-------+--------------------------------+
; Parameter Name ; Value ; Type ;
+----------------------+-------+--------------------------------+
; freq ; 50000 ; Integer ;
; in_phase ; true ; Enumerated ;
; pipe_en ; false ; Enumerated ;
; max_nop ; 10000 ; Integer ;
; multiple_active_rows ; false ; Enumerated ;
; data_width ; 32 ; Integer ;
; nrows ; 4096 ; Integer ;
; ncols ; 256 ; Integer ;
; haddr_width ; 23 ; Integer ;
; saddr_width ; 12 ; Integer ;
+----------------------+-------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/leo/sdramcontroller/11-3/sdram_tb.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
Info: Processing started: Thu Nov 03 20:10:37 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sdram_tb -c sdram_tb
Info: Found 2 design units, including 0 entities, in source file common.vhd
Info: Found design unit 1: common
Info: Found design unit 2: common-body
Info: Found 3 design units, including 1 entities, in source file sdramcntl.vhd
Info: Found design unit 1: sdram
Info: Found design unit 2: sdramCntl-arch
Info: Found entity 1: sdramCntl
Info: Found 3 design units, including 1 entities, in source file randgen.vhd
Info: Found design unit 1: rand
Info: Found design unit 2: randGen-arch
Info: Found entity 1: randGen
Info: Found 3 design units, including 1 entities, in source file memtest.vhd
Info: Found design unit 1: mem
Info: Found design unit 2: memTest-arch
Info: Found entity 1: memTest
Info: Found 2 design units, including 1 entities, in source file sdram_tb.vhd
Info: Found design unit 1: sdram_tb-a
Info: Found entity 1: sdram_tb
Info: Elaborating entity "sdram_tb" for the top level hierarchy
Warning: Output port "led_opBegun" at sdram_tb.vhd(28) has no driver
Warning: Output port "led_rdPending" at sdram_tb.vhd(29) has no driver
Warning: Output port "led_done" at sdram_tb.vhd(30) has no driver
Warning: Output port "led_rdDone" at sdram_tb.vhd(31) has no driver
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