library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use WORK.common.all;
use WORK.rand.all;
use WORK.mem.all;
use WORK.sdram.all;
ENTITY sdram_tb IS
	generic(
      FREQ                 :     natural := 50_000;  -- operating frequency in KHz
      IN_PHASE             :     boolean := true;  -- SDRAM and controller work on same or opposite clock edge
      PIPE_EN              :     boolean := false;  -- if true, enable pipelined read operations
      MAX_NOP              :     natural := 10000;  -- number of NOPs before entering self-refresh
      MULTIPLE_ACTIVE_ROWS :     boolean := false;  -- if true, allow an active row in each bank
      DATA_WIDTH           :     natural := 32;  -- host & SDRAM data width
      NROWS                :     natural := 4096;  -- number of rows in SDRAM array
      NCOLS                :     natural := 256;  -- number of columns in SDRAM array
      HADDR_WIDTH          :     natural := 23;  -- host-side address width
	  ADDR_WIDTH 		   :     natural := 23;
      SADDR_WIDTH          :     natural := 12  -- SDRAM-side address width
      );
	PORT
	(
		clk				: in std_logic;
		rst_n			: in std_logic;
		bt_doAgain_n    : in  std_logic;  -- bt_doAgain_n='0',do sdram testing again
      	led_opBegun     : out std_logic;  -- read/write/self-refresh op has begun (clocked)
      	led_rdPending   : out std_logic;  -- true if read operation(s) are still in the pipeline
      	led_done        : out std_logic;  -- read or write operation is done
		led_rdDone      : out std_logic;  -- read operation is done and data is available        
		status          : out std_logic_vector(3 downto 0);  -- diagnostic status of the FSM         
	  	
		cke             : out std_logic;  -- clock-enable to SDRAM
      	ce_n            : out std_logic;  -- chip-select to SDRAM
      	ras_n           : out std_logic;  -- SDRAM row address strobe
      	cas_n           : out std_logic;  -- SDRAM column address strobe
      	we_n            : out std_logic;  -- SDRAM write enable
      	ba              : out std_logic_vector(1 downto 0);  -- SDRAM bank address
      	sAddr           : out std_logic_vector(SADDR_WIDTH-1 downto 0);  -- SDRAM row/column address
      	sD              : inout  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from/to SDRAM
      	dqm             : out std_logic_vector(DATA_WIDTH/8-1 downto 0);
	    LD				: out std_logic_vector(6 downto 0)
	);
END sdram_tb;
ARCHITECTURE a OF sdram_tb IS
    SIGNAL dIn        :   std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from memory
    SIGNAL rd         :  std_logic;         -- memory read control signal
    SIGNAL wr         :  std_logic;         -- memory write control signal
    SIGNAL addr       :  std_logic_vector(ADDR_WIDTH-1 downto 0);  -- address to memory
    SIGNAL dOut       :  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to memory
    SIGNAL progress   :  std_logic_vector(1 downto 0);  -- memory test progress indicator
    SIGNAL err        :  std_logic;
	SIGNAL tempBegun  :  std_logic;
	SIGNAL tempDone	  :  std_logic;
	SIGNAL tempRdPending	: std_logic;
	SIGNAL tempRdDone :  std_logic;
	SIGNAL earlyOpBegun : std_logic;
BEGIN
	memt : memTest 
	
	PORT MAP
	(
		clk=>clk,
		rst_n=>rst_n,
		doAgain_n=>bt_doAgain_n,
		begun=>tempBegun,
		done=>tempDone,
		dIn =>dIn ,
		rdPending=>tempRdPending,
		rd=>rd,
		wr=>wr,
		addr=>addr,
		dOut=>dOut,
		progress=>progress,
		err=>err
	);
	sdram1 : sdramCntl 
	PORT MAP
	(
		clk=>clk,
		rst_n=>rst_n,
		lock =>'1',
		rd=>rd,
		wr=>wr,
		earlyOpBegun=>earlyOpBegun,
		opBegun=>tempBegun,
		rdPending=>tempRdPending,
		done=>tempDone,
		rdDone=>tempRdDone,
		hAddr=>addr,
		hDIn =>dOut,
		hDOut=>dIn,
		status =>status ,
		cke=>cke,
		ce_n=>ce_n,
		ras_n=>ras_n,
		cas_n =>cas_n ,
		we_n=>we_n,
		ba=>ba,
		sAddr=>sAddr,
		sDIn=>sD,
		sDOut=>sD,
		dqm =>dqm 
	);
	
	
	--testing 
	
	testing:
	--test the sdamController
	--if the LD show "E",it means some error occur
	--if the LD show "0",it means no error occur,the sdramController is ok
	  LD<="0111111" when err='0' else
		  "1111001"when err='1' else
		  "1111111";
	
	
	--indicate the testing process
  	--LD	<=	"0111111" WHEN progress="00" ELSE	--indicate the current controller state is INIT
	--		"0000110" WHEN progress="01" ELSE	--indicate the current controller state is LOAD
	--		"1011011" WHEN progress="10" ELSE	--indicate the current controller state is COMPARE orEMPTY_PIPE
	--		"1001111" WHEN progress="11" ELSE	--indicate the current controller state is STOP
	--		"1111111";							--indicate the current controller state is system error
  
  	--indicate the controller operation process
  	--led_opBegun<=tempBegun;	--indicate the testing operation(s) has begun
  	--led_done<=tempDone;		--indicate the read/write operation(s) has done
  	--led_rdPending<=tempRdPending;	--indicate the read operation(s) are still in the pipeline
  	--led_rdDone<=tempRdDone;	--indicate the read operation is done and data is available
END a;